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An Engineer's Guide to DesignCon: Technical papers
By Staff -- EDN, 2/6/2006
DesignCon will feature dozens of technical paper presentations; here's a small sampling of some of the catchier papers at the show.
On Monday, session TF-MA1 looks at thermal issues in board design, while TF-MA4 examines "Measurement-Based Signal-Integrity Analysis of the Passive Physical Layer."
Session TF-MP1, "Beyond RTL: Advanced Digital System Design," and session TF-MP "From Algorithm to Low-Power Implementation: Optimizing a Ghost Canceling Design for Low Power" also look interesting, as does TF-MP6, "Creating System Databooks Using SPIRIT Consortium Specifications."
On Tuesday morning the folks at Faraday Technology are presenting a paper on "A Fast Methodology for Static Power IP Characterization" in session 1-TA1. In session 4-TA1, the folks from Sun Microsystems are presenting a paper called "Design and Analysis for Variability in Nanometer Technologies."
Later Tuesday morning, Xin Wu of Fluent Inc. is presenting a paper entitled "Impedance Matched Lossy Decoupling for PCB Power Delivery and PCB/Heatsink Radiated EMI Noise" in session 12-TA2.
In session 1-TA2, Metta Semiconductor will be presenting a paper entitled "Low-Power Transport Stream Demultiplexer Architecture with New Secure Format to Remultiplexing Approach."
Altera is presenting a paper called "Functional Verification of a Multi-Gigabit Transceiver IP in FPGA session 3-TA3 Tuesday afternoon.
Meanwhile Ingot Systems' engineers are presenting a paper entitled "Design of a 400- MHz DDR2 Memory Controller for a High-Performance CPU Application" in session 1-TA3.
Also Tuesday afternoon, Intel will present in session 5-TP1 a paper entitled "Frequency-Dependant Physical-Statistical Material Property Extraction for Tabular W-Element Model Based on VNA Measurements."
Apple Computer's Principal signal integrity Engineer Zhiping Yang is presenting in session 5-TP2 a paper called "The Myth about the Ground and How to Correctly Use It in High-Speed Signal-Integrity and Power-Integrity Modeling and Simulation."
On Wednesday, engineers from Rambus are presenting a paper on "Implementation of Broadband Transmission Line Models with Accurate Low-Frequency Response for High-Speed System Simulations" in session 7-WA1.
In session 13-WA2 on Wednesday morning, Intel engineers are presenting a paper entitled "Advanced Package Design Validation Methods Using a High-Resolution TDR and a Commercially Available High-Speed Chip."
Tuesday afternoon, Intel engineers in session 7-WP1 are presenting a paper describing "A Co-Design Methodology of Signal Integrity and Power Integrity."
In session 2-WP2 on Tuesday consultant Brian Baily and G Carina Chiang of RedBear Technology are presenting "Why Did My Chip Do That? A Survey of On-Chip Debug and Diagnosis Techniques."
In session 5-WP2, Texas A&M and Agilent are presenting a paper on "Impedance Matching Techniques for VLSI Packaging."
Thursday is tutorial day at DesignCon. Three tutorials run concurrently through the morning. They are session TF-THA1, "Getting Started with SystemVerilog Assertions," session TF-THA2, "Embedded Capacitance and Embedded Capacitors: Overview on Modeling and Applications," and finally, session TF-THA3, "Multi-Mode, Multi-Corner, Multi-Voltage, Multi-Frequency Design: When, How, and Why."
