News and New Products

Lattice announces 90-nm high-end and economy-class FPGAs

By Michael Santarini, Senior Editor -- EDN, 2/8/2006

Apparently unafraid of going toe to toe with Xilinx and Altera in the high-end SRAM-based FPGA market, Lattice Semiconductor this week will announce a high-performance FPGA aimed squarely at the high-speed-communications and data-storage design spaces. The company is also releasing a new "economy-class" FPGA.

Both new device families enjoy lower power and a density boost compared with previous Lattice offerings, thanks to fab partner Fujitsu's 90-nm process, according to Stan Kopec, the company's corporate vice president of marketing. The previous generation was implemented in a 130-nm process.

On top of the inherent improvements from the process shrink, Lattice has also added several new features to its high-end offering, called the LatticeSC, and to the economy offering, the LatticeECP2.

The theme of the LatticeSC is speed, said Shakeel Peera, product marketing manager. The device suits two of the big-money markets for FPGAs: high-speed communications and data storage.

Lattice has added high-channel-count SERDES (serializer/deserializer) supporting 3.4-Gbps data rates, PURESPEED 2-Gbps parallel I/O, and new clock-management structures that allow the FPGAs' logic to operate at speeds up to 500 MHz, Peera said. One family member also includes precoded structured-ASIC blocks.

A premier feature of the LatticeSC is its use of SERDES blocks, Peera said. The devices in the family offer from four to 32 SERDES channels.

The family will include five products, ranging in density from 15,200 LUTs (lookup tables) or 152,000 ASIC gates in the SC15 to 115,000 LUTs or 1.15 million ASIC gates in the SC115. The LUTs can be reconfigured as SRAM, but the device already has up to 7.8 Mbits of embedded SRAM.

The devices can run from a 1.0 or 1.2V supply. "Users have a choice of maximizing performance or, if they have a very tight timing budget on their boards, they can tune down the supply voltage to 1V, thereby saving about 50% core power," Peera said.

The devices have dedicated gearbox logic for SDR, DDR1, and DDR2. To support the gearbox logic, the SC devices include both PLLs (phase locked loops) and DLLs (delay locked loops). Users can have up to eight PLLs for filtering jitter when driving signals off chip and up to 12 DLLs to track jitter for incoming signals, Peera said.

"Given all these features, the fabric itself runs at about 500 MHz for two to three levels of logic," Peera said.

To help users manage setup-and-hold-time margin at input registers, each LatticeSC I/O pin includes an Input Delay (INDEL) alignment block with 144 taps at 40-psec intervals.

For high-speed, source-synchronous I/O, Lattice has added to the device an AIL (adaptive input logic) that allows users to monitor and control closed-loop pin timing. The AIL feature examines setup and hold times of every input data pin and adjusts the delay until the data edge falls inside the allowable window. The feature allows designs to support speeds of up to 2 Gbps on a single pin, Peera said.

Lattice will also offer a variation of the SC device called the SC-M that adds preconfigured structured-ASIC blocks to the FPGA. The structured-ASIC blocks, which are implemented in the "white space" or unused areas of the SC device, add 50,000 ASIC gates of functionality to the standard SC architecture. The structured blocks add the following functions: flexiMAC 1-Gbps Ethernet, flexiMAC 10-Gbps Ethernet, flexiMAC PCIe (PCI Express), Memory Controller DDR1/2, Memory Controller QDR2, Memory Controller RLDRAM, and SPI4.2.

As for the economy-class LatticeECP2, the second-generation device's key selling point is its relatively low price per LUT, according to Gordon Hands, marketing director for the ECP2 products. The device is expected to sell for $0.50 per 1000 LUTs in high volume a couple of months after release when prices normalize, Hands said.

Lattice plans to offer six devices in the ECP2 family, ranging in density from 6000 to 70,000 LUTs with a top clock of 375 MHz when running simple functions. All the ECP2 devices run at 1.2V.

LatticeECP2 devices will provide between 55 kbits and 1 Mbit of embedded memory through sysMEM embedded block RAM and 95 to 628 I/O pins, which, according to Hands, boosts I/O performance 50% over the previous ECP device, which was implemented in 130-nm technology. The devices also include a pre-engineered 400-Mbps DDR2 memory interface.

"We are also able to offer three times the DSP capacity and have made a number of significant enhancements to the way users can configure the part," Hands said. For implementing DSP blocks, the device has 88 18×18 multipliers. The company has also enhanced its link with The MathWorks to facilitate the programming of DSP functions.

The devices include sysCLOCK PLLs and DLLs for frequency synthesis and clock alignment. Each device has two DLLs and two to six PLLs, Hands said.

"For configuration, we have dual-boot encryption and transparent updates," Hands said. "Dual boot allows the PROM to hold more than one configuration to boot the FPGA. We support the encryption of data in the PROM and decryption of that as it comes into the FPGA."

The devices also have a feature called TransFR (Transparent Field Reconfiguration) that allows designers to freeze I/O states while loading fixes so the device can keep operating while being updated or reconfigured.

Piracy is a key concern in FPGAs, and SRAM-based FPGAs are generally easier to crack and pirate than their nonvolatile counterparts. However, Hands said, Lattice has added advanced encryption to the ECP2. In particular, ECP2 devices have on-chip nonvolatile key storage and decryption circuitry, which allows the decryption of 128-bit AES-encrypted bit streams. The key is created by the FPGA designer and stored in the chip's nonvolatile circuitry, Hands said.

Lattice's ispLEVER design tool suite (version 5.1, service pack 2) supports both the LatticeECP2 and LatticeSC families. The first LatticeSC device is the 250,000-ASIC-gate, 25,000-LUT LatticeSC25, which the company expects to release in volume in the second quarter. The other four devices are slated for later this year. The first commercially available LatticeECP2 device is the ECP2-50, a 48,000-LUT device.