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Panelists: Engineers still suffering from jitter jitters

By Michael Santarini, Senior Editor -- EDN, 2/7/2006

As serial data rates climb past 2 Gbps while voltage falls in many consumer applications, more engineers are experiencing the challenge of trying to locate sources of timing jitter in their designs—while trying to meet the 10^-12 BER (bit error rate) tolerance that managers usually require for high-speed applications.

That's the message conveyed by designers, test-and-measurement engineers, and test-equipment vendors at DesignCon 2006 Monday night, in a panel that kicked off the technical panel track.

The well-attended jitter panel is becoming a tradition at DesignCon. This is the third year engineers have gathered to talk about the growing jitter problem and bounce around ideas and advice. Chris Loberg, marketing manager at Tektronix, moderated this year's panel, which included Maxtor's Eric Kvamme, Agilent's Greg LeCheminant, Wavecrest's Mike Li, LSI Logic's Mark Marlett, Intel circuit architect Andrew Martwick, Tektronix's Kalev Sepp, and Teraspeed Consulting Group's Ransom Stephens.

Even the simplest high-speed design—where all the components (the transmitter, interconnect, receiver and reference clock) meet their individual specifications—can turn into jitter chaos when linked together in a system, Stephens said.

"A reference clock sometimes drives a receiver and sometimes the clock is reconstructed from the data," he said. "Whatever happens though the noise and jitter on the reference clock appears everywhere." The trouble arises from engineers "thinking [that] noise from the clock is the source of the problem," he added.

"None of the effects are independent," he said. "If a certain amount of intersymbol interference is introduced by the interconnect, it will drive the receiver in a different way, even if the net intersymbol interference is the same. In other words, the jitter and noise on each component are correlated. Thus, when we spec individual pieces independently, we are kidding ourselves."

Although extra jitter from the sum of all of a system's good components can cause problems, engineers also face the complex task of testing and validating the individual components. Transmitters are hard to validate because their physical behavior is nonlinear and not symmetrical, LSI's Marlett said. "In talking about system interaction, my first question is, if the transmit driver is not linear, what does that mean for ISI [intersymbol interference], random, and periodic jitter?"

Small changes in channel resonances can cause jitter and increase BERs in eye-diagram testing, Marlett said. He added that a reference clock is more complex with spread-spectrum clocking, where jitter transfer and jitter generation can cause greater jitter down the line in other system components.

As date rates go up and the channels get longer, eventually designs are going to reach a point where eye diagrams are going to start to close down, said Agilent's LeCheminant. "When that happens, testing of transmitters is going to become difficult," he said.

When eye diagrams collapse due to factors like ISI, designers can then start to shift some of the burden of recovering the system to the receiver by performing equalization, LeChaminant said. "If 'good' is difficult to define in this era of closed eye, it is also going to be even more difficult to test," he said.

Receiver testing isn't a breeze either. Tektronix' Sepp outlined testing schemes and experiments for full characterization and component testing. At its most basic level, receiver testing involves introducing stimuli to receiver waves, then recording how the device or system behaves. More complex systems require use of hardware such as calibrators and oscilloscopes in addition to a "test-outcome detector," he said. The detectors range in ability from counting the number of errors found to performing loop-back analyses to identify error types, Sepp said.

Panelists suggested that one way to handle jitter is to simply require more rigid and detailed jitter specifications.

However, creating a top-level jitter specification is difficult because you must do so without knowing who is going to create the parts, Maxtor's Kvamme said. For example, serial ATA defines total jitter and then deterministic jitter as a single limit, and has about seven patterns for testing, he said. "But what it doesn't define is how that deterministic jitter is built and what are the spectral components of that deterministic jitter," Kvamme said. "…In a real system there are an enormous number of patterns that are possible to generate. There is an infinite number of different ways you can create realistic total jitter and deterministic breakdowns." And most engineers don't have time to do that much testing.

Intel's Martwick, one of the authors of the 3GIO physical-layer specification and a cochair of the PCI Express jitter working group, said that high-speed specifications, while not the greatest for engineering and validation, mainly serve to ensure that devices from two different vendors will be interoperable. Engineers shouldn't overlook opportunities to check compliance and interoperability at "plugfests," which help them ensure their systems work with many vendors, Martwick said. To facilitate that process, engineers should design their systems so that compliance testing can be observed with simple equipment, he said. Engineers should think ahead to testing during the design phase to ensure their system cards don't require extra soldering, that they snap into vendor systems, and that they have observable ports, he said.

Fault coverage is another key to jitter testing, said Wavecrest's Li, whose company sells testers.

In the Q&A portion of the session, panelists debated whether or not the longstanding BER tolerance metric of 10^-12 should be more flexible and application specific. For example, panelists suggested the metric could be more lax—say 10^-8—for less critical applications, but should probably be even higher for data-intensive and mission-critical applications. Stephens joked that he hoped his banking network employs BER requirements upwards of 10^-16.