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ISSCC offers divergent views of SOC future
By Ron Wilson, Executive Editor -- EDN, 2/8/2006
Keynote addresses and papers at the 2006 International Solid State Circuits Conference in San Francisco this week showed that SOC (system-on-chip) integration is far from the simple march to a single chip that has often been portrayed. Rather, the conference unveiled a complex dance, choreographed by market need and engineering necessity, in which features and functions come and go—now integrated, now separate; now in dedicated hardware, now in software; but always on the move.
After a detailed introduction to the roadmap for trans-90-nm processes from IBM fellow T.C. Chen, back-to-back invited papers by Hermann Eul, a member of Infineon's management board, and Ken Kutaragi, Sony Computer Entertainment president and CEO, illustrated the course of SOC integration from two divergent points of view: wireless radio and game devices, respectively.
Using Infineon's "single-chip" GSM/GPRS cell phone—an SOC that provides most of the active devices in a handset except for the power amplifier and antenna switch—Eul argued that integration of the digital baseband and application processors was not the end of the road for 90-nm technology. By careful rethinking of how functions should be divided up between the digital and analog domains, by aggressive use of digital circuits to correct for the shortcomings of 130-nm analog circuits, and by what Eul later referred to as "some special features in the CMOS process to address the noise figure," Infineon was able to move the low-noise amplifier, local oscillator, down-converter, data converters, and audio amplifiers onto the same die with the baseband and application-processor blocks.
Debate raged for a long time within Infineon over whether to attempt integration of the RF devices into the low-cost handset SOC, Eul noted. "In the end, we just did it, and it works," he said. "There is a danger in debating too long. At the beginning of a project the risks are often obvious, but the benefits not so much so. For instance, we knew that integration would increase die size, and moving some functions to digital might increase power. In the end, integration substantially reduced external parts count—a big cost factor in this segment. And the power is competitive. Maybe it is higher for some functions, but at the end of the day only the total system power counts."
The handset chip makes use of numerous dedicated processing blocks. But the trend is in another direction, Eul suggested. The dual demands of uncertain standards, which require heavy reliance on software to implement functions, and low power, which dictates use of parallelism to reduce clock frequencies and operating voltages, suggest a move from monolithic CPUs and DSPs surrounded by accelerators to an array of similar processors.
"I believe that the move to multicore approaches is a trend, not a passing thing," Eul said. "The software for multiprocessing—at least in applications with high data parallelism—has improved enormously. Today, once the architecture understands what needs to be done, it is possible to find a solution.
"But that doesn't imply the end of special-purpose accelerators," Eul added. "Today we use accelerators for specific, well-defined functions like encryption or error correction in conjunction with processor clusters. I think a completely 'clean' cluster of processors without specialized hardware would not survive in the market."
Even though analog integration is becoming increasingly difficult, the future includes more of it, according to Eul. The cluster of LDOs, amplifiers, boost regulators, and other circuits that today are crammed into a single analog chip make up a next target for integration. "One of our goals is to make the circuitry for power management and many of these other analog functions implementable in mainstream CMOS," Eul said. It appears achievable for most things—maybe not for the boost regulators."
In contrast, Sony's Kutaragi described the path his corporation has taken from the earliest PlayStation chips to the much-described Cell processor in the PlayStation 3. Kutaragi outlined the decision to rely on embedded DRAM on the graphics engine to meet bandwidth requirements, and how the company stayed with that decision through several levels of integration, ending in the single-chip RISC processor and graphics engine combination in the 2004 handheld version of the PlayStation.
But with the PlayStation 3, Kutaragi described a radical departure—from a RISC CPU surrounded by specialized hardware engines and embedded DRAM to the nearly symmetric cluster of floating-point vector processors in the Cell chip. The ability to parallelize graphics tasks had made it possible to reduce reliance on specialized engines.
But here Kutaragi sounded the same reservation as Eul, albeit more quietly. Although, according to some sources, the PlayStation was originally conceived as doing its own graphics rendering in a version of the Cell processor, the architects eventually turned to a specialized rendering/shading chip. And there would be other cases in which the move to multicore solutions and software would be at least delayed. "We believe that hardware-level security is fundamental," Kutaragi said. "Software solutions may be not fast or robust enough to protect the system and its content when it is connected to the global network environment."
Even with the trend toward processor clusters, hardware accelerators will play a role. And the trend toward digitalization notwithstanding, the analog content of SOCs is likely to increase. At least that is the trend as seen from these two markets.
