News and New Products

VIA shrinks for embedded market

By Ron Wilson, Executive Editor -- EDN, 4/6/2006

The attractions of the personal computer architecture for embedded developers are many: proven hardware, relatively complete systems designs, high performance per dollar, and that huge base of software development tools and programmers. But one of the big disadvantages, despite numerous attempts at compact designs, has been form factor: PC motherboards are big.

In part, this is because there is no particular reward for small form factors in the mainstream PC business. In part, it is also because of the increasing problem of dissipating all the heat generated by those trans-gigahertz CPUs and their fast caches.

VIA Technologies at the Embedded Systems Conference this week showed a number of alternative approaches to dealing with the form-factor problem, some conventional and some reaching toward new technology. All are based on the facts that VIA sells both x86 CPUs and chip sets, and on their ability to operate at quite low power levels—about 7.5W for the CPU and about 2.5W for the North/Southbridge chips.

One such step is the introduction of a combined Northbridge/Southbridge device. As VIA product marketing manager Johnny Wang explained, combining the two chips has no real benefit for desktop or notebook personal computers, which have defined form factors. But in VIA’s embedded markets, the combination opens possibilities for industrial form-factor boards, including PC-104, which consortium the company has just joined.

Technologically the combination presented no major technical challenges, according to Wang. It involved moving functional blocks from both the VIA Northbridge and Southbridge chips onto one die, and replacing the proprietary high-speed link between the two chips with on-die interconnect.

Planning the pad ring, however, presented a practical challenge. Simply replicating all of the I/O pins from the two chips—without the inter-chip connection, of course—would yield a high pin-count device that would have caused users problems in real estate, routing and cost. Instead, VIA chose to selectively leave out interfaces from the Southbridge portion of the chip that they felt were less relevant to very small embedded designs. This meant reducing the number of ports of some types, and removing the legacy PCI-bus interface.

In parallel with this effort, VIA is exploring system-in-package technology as a route to greater board density. Initial efforts in this area have included packaging CPUs with both two-chip and single-chip core logic products in side-by-side dual-die packages. Wang said that the heat dissipation requirements of the CPU and even the core logic dice made side-by-side preferable to stacked packaging, which would reduce board footprint even further but would require very careful thermal management.