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New version opens multicore doors for HyperTransport

By Ron Wilson, Executive Editor -- EDN, 4/24/2006

HyperTransport, the physical-layer interchip-communications standard whose claim to fame has been its use on Advanced Micro Devices CPU chips, has rolled out its most recent revision, HyperTransport 3.0. The new spec substantially changes the capabilities of the interface, broadening its applicability and positioning HyperTransport as a foundation technology for the future of board-level multiprocessing.

Fundamentally, HyperTransport has been an elegantly simple concept: 16 data lines plus clock-signal and sideband-control-signal pins, all running synchronously using LVDS (low-voltage differential signaling). Running at a 1.4-GHz clock rate, the 2.0 version of the specification offered both high peak data rate and low latency, which is important for the kinds of short-haul, chip-to-chip backbone applications that it targets. As a thin, point-to-point-interconnect layer, HyperTransport can transfer a string of packets with nearly as little fuss as simple point-to-point wiring but at much higher speeds then would be possible for individual asynchronous links.

This virtue led to AMD’s decision to adopt HyperTransport for inclusion on the company’s recent CPU designs, serving as the link between the CPU and the north bridge and, more significantly for the future, the link between CPUs, both on the die in the dual-core Opteron and between chips in board-level multiprocessing servers. AMD also uses the link to connect accelerator cores to the CPUs.

HyperTransport 3.0 aims at furthering this kind of thinking in the multicore world. The most obvious difference from 2.0 is a faster maximum clock speed: 2.6 GHz. This increase allows aggregate throughput over a 16-bit link of 20.8 Gbytes/sec. This change in turn demands increased complexity on both the transmitter and the receiver sides of the connection. The transmitter gets enhanced training patterns to cope with the multibit skew that can occur at these speeds. It also now can employ scrambling to ease the receiver’s recovery job. The receiver has added equalization capabilities and can use clock-based phase alignment to undo multibit skew in the interconnect medium. Along with these new features, the new version retains 100% compatibility with previous operating modes.

The 3.0 specification also retains HyperTransport HTX—the ability to operate at longer distances and through a standard connector. This feature permits designers to create a HyperTransport link to a daughtercard, allowing plug-in accelerator cards. The spec also retains a hot-swapping feature with a nod toward the online-maintenance needs of server farmers.

These features also have demanded new technology at the higher clock rate. Under the new standard, a HyperTransport interface must sense when it is capacitively coupled to its partner through an HTX link, as opposed to directly wired to the partner through a standard chip-to-chip link. If the HTX link is in use, the interface must shift to an 8b/10b-coding scheme. This requirement means that the receiver must execute a more complex clock-recovery algorithm.

Concurrently with the release of the specification, the HyperTransport Consortium is expected to announce that GDA Technologies is developing HyperTransport 3.0-interface IP (intellectual property). Extensive discussions have taken place with AMD—a major player in the new spec—and with accelerator vendors and FPGA leaders.