Many of today's high-speed serial designs use embedded clocks to avoid routing and timing issues involved with separate data and clock signals and to free up precious real estate on board designs. These embedded clocks are not separate clock signals coupled to the original data signal. Instead, the clock times the data-transmitter output, and a separate PLL recovers the clock signal from the data at the receiver. Because the data is a synchronous source of electrical energy, the clock frequency of the data focuses at half the data rate and other transition-period harmonics and creates EMI (electromagnetic interference) at those frequencies. EMC (electromagnetic-compatibility) labs use broad-spectrum analyzers to measure the EMI of a device in discrete bands—120 kHz wide, for example—when determining compliance.

Many device vendors have now turned to SSC (spread-spectrum clocking), a method of data-rate smearing, to avoid having too much EMI within any one band when an EMC tester tests the equipment. SSC further helps to reduce crosstalk between adjacent asynchronous buses in complex systems, such as PCs or servers, in which many high-speed serial peripheral buses operate simultaneously. You implement spread-spectrum clocking by frequency-modulating the data-transmission output of a transmitter to spread the spectral-energy peaks out over a wider bandwidth. The total energy on the bus, therefore, does not decrease but spreads over a wider frequency band. A PLL at the receiver then uses a closed-loop highpass-filter function to track the frequency modulation of the SSC and recover the data. You need to measure your SSC's implementation accuracy using a high-speed real-time oscilloscope with clock-recovery capability and a measurement-trending software package.

It is important to consider the methods available to get a multigigabit signal from a design without disrupting the signal's voltage and timing characteristics. Many designers allot enough space to load SMA connectors onto their development boards to directly measure the transmitted signal using an oscilloscope. This practice is usually a good one to use early in chip-set validation, but it may be impossible once the board goes to final layout for production prototyping. At this stage, it is crucial to have robust, high-performance test tools available to debug your target system and allow for precision measurements at either the transmitter or the receiver end of a high-speed serial link. Today's state-of-the-art differential active voltage probes now offer as much as 13 GHz of measurement bandwidth with less than 0.22 pF of capacitive loading at the probe tip. These tools typically employ small, passive test circuits with miniature connectivity to the device under test and an active amplifier to transmit the signal with minimal distortion back to an oscilloscope for viewing.

Figure 1 illustrates a small, 13-GHz differential active voltage probe that connects directly to the package pins of a high-speed, differential transmitter on an active link. You should use the highest bandwidth probing tool available to avoid inducing unwanted slew-rate limitations or artificial signal anomalies into the signal under test. Some high-speed serial-link standards additionally specify compliance-test points, which typically appear at a common connector interface in which the high-speed serial transmitter pair mates with the corresponding receiver pair of a similar device to which it connects. An example would be the SATA (Serial ATA) electrical-compliance interface, which measures the electrical characteristics of the transmitter at the SATA connector, because it connects to a high-quality laboratory load. A high-bandwidth oscilloscope and reference-quality test connector provide the high-quality load. The equipment has greater than 20 dB of return loss at 5 GHz and 10 dB of return loss at 8 GHz. Figure 2 illustrates this type of laboratory load for SATA electrical-performance validation and compliance testing.

Once you have established an appropriate connectivity method to properly terminate and capture the signal under test, you can measure the SSC modulation depth and frequency. You should use a repeating "1010" data pattern to test the SSC's performance, and you should send the repeating data pattern at the highest supported data rate for the bus. This approach ensures that the spectral content of the digital signal focuses primarily at one-half the data rate and reduces the effects of data-dependent jitter in the measured data rate. You should also select an oscilloscope with at least enough bandwidth to capture the fifth harmonic of the nominal data rate and enough sample rate to avoid aliasing on a single-shot data capture. For 3-Gbps SATA, this requirement would involve an oscilloscope bandwidth of no less than 7.5 GHz and at least 20G samples/sec of single-shot sample rate. The SATA electrical specification recommends 10 GHz of bandwidth, and a common rule for digitizing oscilloscopes is that the minimum sample rate should be 2.5 times the oscilloscope bandwidth to avoid aliasing of frequencies near the oscilloscope's upper bandwidth limit. Several real-time oscilloscopes are now available that meet the 10-GHz and 25G-sample/sec minimum requirements to most accurately measure the SSC profile of 3-Gbps data streams.

You can easily measure the accuracy of SSC using a real-time oscilloscope with deep memory and a jitter-measurement package that can recover a clock and can trend the measured time gaps between the transitions in a fast serial data stream. You must first evaluate the repeating frequency of your SSC modulation and find a digitizing, real-time oscilloscope with enough memory to capture at least one full period of the SSC's modulation frequency at its maximum sample rate, which is 40G samples/sec on today's highest bandwidth real-time oscilloscopes. For example, if you have a 33-kHz frequency modulation on a 3-Gbps data rate, then you will need approximately 2 million points of memory at 40G samples/sec (2 million samples×25 psec/sample=50 µsec) to capture the 30.3-µsec modulation period of the SSC. Figure 3 shows a 33-kHz, triangular SSC modulating a 3-Gbps data signal. The triangular SSC profile downconverts the data signal's frequency from 0 to –0.5% to reduce the concentration of EMI at any one frequency. This action limits the data rate to 2.985 to 3 Gbps, translating to a change of 0 to –15 MHz from the nominal line rate.

This 13-GHz, real-time oscilloscope includes the EZJIT measurement-trending and jitter-analysis software, which allows designers to observe the change in the data rate of the data that this link is transmitting, as well as the frequency accuracy of the 33-kHz, triangular-SSC profile that is frequency-modulating the data. A simple trend measurement of the data rate shows all variations in the data rate due to both the SSC-frequency modulation and as short-term variations in the data rate, which can make it difficult to accurately measure the SSC profile. Therefore, most high-speed-serial-bus specifications that allow transmitters to use SSC specify a narrower frequency range over which to measure the SSC's modulation depth and frequency accuracy. The SATA electrical specification specifies a lowpass filter that you must apply to the measurement trend with a cutoff frequency of 60 times the maximum frequency, or approximately 1.98 MHz, for the triangular SSC.

The real-time oscilloscope offers a smoothing feature in its measurement-trending-software package that acts as a lowpass filter for removing higher frequency variations in the data-rate trend. Sources of data-dependent, random, or bounded uncorrelated jitter above the desired 1.98-MHz cutoff frequency cause these variations. As a general guideline, a 3-Gbps SATA link using a 1010, or high-frequency-data, pattern and having a desired cutoff frequency of 1.98 MHz would require 335 smoothing points.

Because the measurement trend plots the data rate on the vertical axis versus time on the horizontal axis, you can use the oscilloscope's automated amplitude measurements to measure the minimum and maximum line-speed rates over an entire cycle of the SSC-modulation period, which in this case is nominally 30.3 µsec. Additionally, you can apply the oscilloscope's automated frequency measurement to the data-rate-measurement trend and adjust its thresholds to measure the frequency at the 50% threshold of the rising or falling edges of the filtered triangular-SSC profile. Figure 3 illustrates several automated oscilloscope measurements that quickly and accurately identify the maximum and minimum data rates of the measured data, which the triangular-SSC profile modulates, as well as the repeating frequency of the SSC profile. The oscilloscope's markers automatically track the frequency measurement, but they can also track the maximum and minimum data-rate measurements. Automated oscilloscope measurements provide a significantly more accurate assessment of the SSC's modulation depth and frequency than traditional methods of manually adjusting data markers.

Correctly setting up and measuring SSC's profile-modulation depth and frequency accuracy is simple with today's state-of-the-art, high-performance oscilloscopes and automated measurement-trending software. You must carefully choose your connection to the transmitter and the appropriate bandwidth and sample rate of the measuring oscilloscope to ensure the integrity of the data signal and the proper reference test load. You must also apply an appropriate lowpass filter to remove higher-frequency-modulation domain "noise" from the measurement trend, exposing only the signal characteristics of interest on the SSC profile you're measuring. In addition, automated amplitude and frequency measurements from the oscilloscope's measurement menu provide simple and accurate measurements of maximum and minimum data rates and SSC-profile frequency, saving you valuable time.