Scaling: a balanced view, part two

In the last installment of Analog Domain, I began a summary of Klaas Bult's analysis on the effect of technology scaling on power dissipation (reference 1 and reference 2). This column replicates the minimum-circuit model and Bult's Algorithm for reference (figure 1 and figure 2 ). The algorithm depends on three process-dependent quantities and eight application-dependent parameters. It calculates six circuit measures, the last of which is the minimum power dissipation for the minimum circuit. Bult's analysis does hang on a few assumptions, but more than a decade of silicon-process history supports them, as do the foreseeable trends in silicon-process development.

The first value to calculate is the maximum V_DD. Ignoring the slight rise in the apparent dielectric strength of ultrathin films compared with thicker film and bulk samples, V_DD is essentially proportional to gate-oxide thickness, T_OX. T_OX, in turn, scales directly with the process's minimum feature size, L_MIN, by a ratio that has held essentially constant over process evolutions that saw L_MIN decline from 3 microns to 60 nm:

The application determines the necessary dynamic range:

where V_UNWANTED refers to the various voltage-error terms, including white noise, 1/f noise, and offset.

Though V_UNWANTED results from the combination of multiple sources, often in practice one term dominates. As a result, the load-capacitance calculation depends on which term is most important to the application.

Applications that are sensitive to offset voltage require a high degree of device matching. Below the 700-nm node, the minimum capacitance to attain a given degree of matching varies in proportion to1/L_MIN. (Calculations are available in Reference 2.) The minimum capacitance for a given dynamic range for circuits in which either white noise or 1/f noise is the dominant consideration varies as 1/L_MIN ². At the 90-nm node, the minimum capacitance for matching is about 200 times larger than the minimum capacitance for white noise, which is about 200 times larger than the minimum capacitance for 1/f noise. For this reason, circuits that demand a high degree of dc accuracy often use device averaging and offset-cancellation techniques.

Given the minimum capacitance that the circuit requires to attain the specified dynamic range, you can calculate the drive current necessary to meet bandwidth, slew-rate, settling-time, and distortion criteria. The next installment of this column will pick up from here.