News and New Products

TSMC shows roadmap details at symposium

Foundry details progress and potholes on road to 65- and 45-nm processes.

By Ron Wilson, Executive Editor -- EDN, 5/19/2006

In a presentation at TSMC's Technology Symposium in San Jose, CA, Wednesday, Shang-yi Chiang, the company's senior vice president for R&D, described the road ahead—and some of the potholes—in the foundry's technology roadmap.

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Following the recent announcement of availability of the company's 65-nm low-power and general-use logic processes, Chiang's discussion focused on the differences between 90 and 65 nm and the challenges ahead as the company looks toward 45-nm process announcements in 2007. Chiang also underlined the importance of two optical-shrink process half-nodes, 80 nm and 55 nm, for customers wanting to arbitrate between advanced process availability and time-to-market for their own products.

From his vantage point in R&D, Chiang spoke of 65 nm as a proven success, saying that more than 20 customers have engaged with the process, and that the first volume production should start in the second half of this year.

The ability to provide both high performance and low power at the system level has led to increased complexity in the 65-nm processes, Chiang said. The company provides three different transistor types with low, medium, and high threshold voltages. This allows the designer—skills and tools permitting—to use fast high-leakage transistors only on critical paths, and to sharply reduce the leakage current on the majority of nets without having to resort to power gating, variable back-bias, or other such complexities.

Even with the use of leaky low-threshold transistors, the increase in performance TSMC has been able to achieve in the 65-nm process does not arise only from geometry scaling, Chiang indicated. The company uses strain engineering extensively in the process to improve channel mobility, he said.

The process has put a lot of strain, in a different sense, on the company's modeling efforts, Chiang reported. TSMC has modified transistor models to include well-proximity and channel-length effects not modeled at 90 nm. In addition "we have heard loud and clear from our customers that we need to improve our analog/mixed-signal and RF models," Chiang said. "We are working on it."

As it did at the 90-nm node with the introduction of an optical shrink to produce an 80-nm offering, TSMC expects to introduce a half-node process on the heels of 65 nm. The company expects to release a 55-nm general-use process near the end of 2006, providing some of the density improvement of 45 nm, but with an optical shrink that will preserve most of the characteristics of the 65-nm G process.

Looking on toward 45 nm, Chiang outlined the major differences compared with the 65-nm node. Unlike the move from 90 to 65 nm, which entailed almost no major materials or technology changes, the move to 45 nm will require introduction of a new lower-k interlayer dielectric material and the introduction of immersion lithography. Neither move is without risks, he said. New materials always require attention to a huge range of issues, from chemical compatibility in the fab to mechanical compatibility with back-end processes. And immersion lithography, while improving depth of field, also creates significant new sources of potential defects. In both cases Chiang expressed optimism, announcing that TSMC is for the first time seeing single-digit defect densities from its immersion-litho step.

Unresolved problems still exist at 45 nm as well, he admitted. A major one is that the company still has not settled on a high-threshold transistor design for the node.

However, for the time being the foundry has dodged a bullet regarding the conversion to high-k gate dielectrics and the accompanying introduction of metal into the gate stack. Chiang said he does not expect TSMC to make this move until it reaches the 32-nm node.