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TI lifts curtain on 45-nm process
By Ron Wilson, Executive Editor -- EDN, 6/12/2006
As the independent foundries begin to announce commercial availability of their 65-nm processes, Texas Instruments—always anxious to let customers know early where it is going—used the forum of the Symposia on VLSI Technology today to give an early look at its 45-nm process.
More than a roadmap but short of a product release, the announcement provides a look into the technological decisions a foundry must make to balance the competitive pressures of the CMOS business, the needs of design teams, and the realities of increasingly unyielding physics.
Although it relies heavily on previous technology, TI's initial 45-nm offering will rest on one major technological change: immersion lithography. Immersion is a primary innovation, making possible finer geometries and, hence, with careful process integration, higher density and somewhat greater performance—all of which TI feels it needs to support its ambitious future plans for IC products. However, according to Ben McKee, TI's vice president of CMOS-technology development for 45-nm processes, immersion lithography is one of the most significant risks in the new process plan. "Immersion lithography is coming together very late in the game," McKee says. "That situation leaves us little time to integrate it into the overall process."
Beyond the huge step of new lithographic equipment and materials, most of the changes TI anticipates in the first version of its 45-nm process are evolutionary. Isolation will use essentially the same module the company uses for its 65-nm process but with a new deposition technique to improve filling. Gate dielectrics will be thinner, and the process will use more nitride. This incremental increase changes films that other TI high-performance processes are already using, McKee says. One other new step will be the decrease of annealing times to milliseconds.
The transistor channels are also in for more evolution. TI will add an epitaxial silicon-germanium layer to increase strain for higher mobility. This change will enhance the liners, caps, and other techniques the company employs at 90- and 65-nm processes. "Once you use a technique, you can't back it out to make room for something better," McKee observes. "You have to keep what you are doing and add to it."
TI will also move along the evolutionary curve in intermetal-dielectric materials, going from their current organosilicate to a second generation of the same material, and improving bulk k from 2.9 to 2.5. Integrating this material with the other layers in the interconnect stack provides an effective k of about 3. TI has also spent time re-engineering the upper metal layers of the interconnect stack to help minimize IR (current-resistance) drop on circuits that can experience huge current transients during operation.
Process variation hovers menacingly over all these changes. TI must ensure that the process-design team provides the chip-design teams with sufficient understanding of systematic variations. The process's approach to strain engineering illustrates the tension between these teams. Increasingly complex strain-inducing mechanisms mean greater potential carrier mobility in the transistors. But they also make the transistor's performance more heavily dependent on its physical surroundings. Designers must use finite-element modeling to examine the structure of groups of transistors to determine the strain on—and, hence, the performance of—each one. The effects of nearby structures on transistor performance are no longer theoretical; cell designers must model them. But limiting the impact of these effects to the cell level, so that IC-cell-placement tools need not take them into account, is a major effort. "You can't just make the die arbitrarily bigger to keep adjacent cells from influencing each other," McKee says. "You have to be careful in where you spend your area budget within the chip."
Similarly, a host of factors, including CMP (chemical mechanical polishing) variations, edge roughness, and even quantum effects, conspire to increase resistance and capacitance variations in the metal. TI has worked to balance these increasing problems with increasing advances in offsetting areas—for instance, by improving control over metal thickness as each layer of metal necessarily gets thinner with decreasing metal pitch.
If you've been following discussions on advanced processes, you might be surprised at the conventionality of the TI plan. Where are the ultra-low-k intermetal dielectrics? What about the metal gates and high-k gate dielectrics? What about FinFETs? The answer is evolution. The initial release of the 45-nm process, which TI plans for next year, will focus on improved component density rather than performance. It will use conventional polysilicon-gate transistors with nitrided dielectrics and conventional strain-inducing techniques. Then, in phases, probably starting a year after the initial introduction, TI will bring in new modules to create high-performance options on the process. These will include silicon-germanium strain layers, fully silicided polysilicon gates, and increased dielectric-nitride levels. The company does not discuss the advent of either high-k materials or novel transistor structures.
TI has built and characterized transistors and is working on an SRAM cell for the process. McKee describes development of the SRAM cell as a delicate balancing act between the reality of lower operating voltage, the consequent need for lower threshold voltage to deliver adequate performance, and the demand for adequate noise margin to maintain reliability. The company is now working with 193-nm steppers, and immersion steppers should join the program this year.
So why is TI describing the process now? Partly, one suspects, the company has a tradition of being the first to give a substantive account of its plans at a new process node. More important, however, in this era of deep interaction between process integration, tool development, model development, and cell design, it is time to start relaying process decisions to the modeling teams, cell designers, and early adopters, who will be responsible for taming the process into something that will perform at the bidding of chip designers. Even with conservative technological choices and complex engineering at the device, circuit, and subsystem levels, this task is daunting.
