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NEC surprises with aggressive 55-nm process
Calculated gambles could put company on par with, or ahead of, competitors moving to 45 nm.
By Ron Wilson, Executive Editor -- EDN, 6/14/2006
NEC Electronics came quickly out of stealth mode last Friday with the announcement of a 55-nm CMOS logic process. The new formula, for which the company already has designs in progress, is less than a full 45-nm process but much more than a typical half-node shrink of the existing 65-nm process.
By introducing new materials and equipment while preserving most of the modules and device structures from 65 nm, the company hopes to have an important alternative in the hands of its designers before 45 nm is ready for prime time. Simultaneously, the company expects to learn about production of two critical new technologies: immersion lithography and high-k gate dielectrics.
The process will provide engineering samples of NEC-designed SOCs by the summer of 2007, with production later that year, according to NEC Electronics America senior design engineering manager Hideya Horikawa. That schedule will coincide with Texas Instruments' rollout of its 45-nm process (see "TI lifts curtain on 45-nm process," 6/12/2006), so comparisons are very much in order.
At first glance, both companies rooted their process designs in conservatism, taking as few risks as possible in venturing away from what is beginning to look like a solid 65-nm platform. TI has chosen to initially focus on density, calling on 193-nm immersion steppers for increased feature density and the next generation of low-k intermetal dielectrics to help with parasitics. In mild contrast to that strategy, NEC has focused instead on standby power and performance for its initial offering. The company has, like TI, chosen to introduce immersion lithography into its 55-nm formula, but has not driven the design rules all the way to 45-nm gate lengths. It has instead taken a step where TI fears quickly to tread, introducing a version of high-k gate dielectric materials into its process.
NEC took even this apparently radical step in a measured way. Rather than using an entirely novel gate design, NEC is applying an HfSiON high-k film in an extremely thin layer over a conventional silicon dioxide layer, Horikawa explained. In this way, the effective value of k for the dielectric stack increases significantly, but the gate work function can be managed without introducing metal in place of polysilicon, Horikawa added.
The approach leads to a chain of serendipity. The high-k gate dielectric permits higher threshold voltage, which in turn lets NEC reduce the impurity concentration in the channel region, resulting in lower GIDL (gate-induced drain leakage). This in turn makes it practical to use reverse body bias—a technique many vendors had feared would not work below 65 nm—to substantially reduce sub-threshold leakage.
The result, Horikawa claims, is a 55-nm transistor that nearly matches the leakage current specifications the ITRS Roadmap sets out for 45-nm transistors, while still delivering 20% to 30% higher drain current than the current 65-nm device. Horikawa said that taken all together, the transistor changes would result in a typical digital baseband SOC chip with 1/10 the standby power consumption of a chip done with conventional transistors, presumably at 65 nm.
These changes have allowed NEC to reach its performance goals without taking another step TI has planned, the introduction downstream of further strain engineering into the transistor. Unlike TI, which plans to introduce the dreaded GaAs material into its process in a late-2007 or 2008 speed enhancement, NEC will stay with the same SiN film technology used at 65 nm.
The focus on gate stack engineering has preserved so much of the transistor geometry, according to Horikawa, that most of the library structures in the new cell libraries NEC is producing for the process will in fact be geometric shrinks of their 65-nm counterparts. The library will contain some new designs as well. By maintaining this conservative stance at the device level, NEC hopes that its existing design-for-manufacturing guidelines will suffice for keeping process variations under control.
It is always a risk introducing a half-node process in the competitive CMOS world. But NEC, with a clear view of the mobile, power-sensitive products it intends to serve, has chosen a calculated set of risks that could put it on par with—or ahead of—competing 45-nm offerings, and put it in the market earlier than most. It is a conservative strategy, but one that could pay off enormously if a few key competitors stumble in their aggressive 45-nm plans.
