IDT adds preprocessing to SRIO switch for base stations

Device offloads some tasks from DSP and chip-rate hardware.

By Ron Wilson, Executive Editor -- EDN, 6/20/2006

The architecture of cellular base stations is gradually coalescing around a common theme. A bank of RF front-end cards sends packetized sample data, generally through SRIO (serial RapidI/O) to an ASIC or FPGA that acts as a fairly simple switch, routing the packets to a waiting bank of DSPs and control-plane processors at the direction of the control plane. This growing consensus begs for an off-the-shelf SRIO switch to form the hub of the processing backplane. And several vendors have been quick to the rescue. But as SRIO switches for this application become more widely used and enter a new generation, competing on just speed and cost isn’t going to accomplish much. So, at least one vendor, IDT is trying to differentiate by adding functions to the switch chip.

But where to find useful functions? IDT’s solution was to examine the processing tasks the DSP chips and chip-rate hardware connected to the fabric are handling and see whether there were some simple, commonly occurring tasks during transmitting and receiving operation. As you might expect from the title of this article, the answer is yes. Both in-sample data manipulation, such as sign extension and endian conversion, and multipacket operations, such as multicasting, reordering of samples, and summation across samples occur, some in the high-speed chip-rate processing hardware and some in the symbol-rate operations on the DSP chips. Because these operations are relatively standard, don’t change with time or context, and occur with some frequency, IDT removed them from the chip- and symbol-rate hardware and moved them into dedicated hardware inside the switch chip.

According to IDT Senior Product Manager Bill Beane, when you present this scenario to the base-station-design team, the hardware engineers typically react with “That’s nice, tell me about the aggregate data rate again.” The software team leaders, however, are immediately interested in the offload capability. Anything routine that they can move out of DSP code means more code space and more execution time for the hard parts.

So, IDT today announced just such an SRIO switch chip (picture). The chip supports 40 SRIO lanes at speeds as high as 3.125 Gbps each. You can group the lanes in clusters of four, and you can configure the drivers to support either chip-to-chip or backplane-SRIO interconnect. The chip also supports SRIO-standard priority and queuing algorithms to manage data flow in what can become complex multichip conversations. The chip also supports the standard’s error-management and maintenance functions.

The competing needs for performance, small die, and manageable power dictate a mesh configuration for the switch fabric. Power, incidentally, is a big issue in the design—not because it is excessive, but because it is so dependent on the usage scenario. Beane says that a good portion of the design effort went into modeling processing topologies and algorithms and examining the data flow and power consumption for each.

The offloaded processing tasks take place in a block that sits parallel to the switch fabric between banks of input and output arbiters. The block comprises 10 identical register-programmed state machines; input and output buffers surround these machines. Each state machine can perform in-sample, multisample, and summing operations, and all 10 machines can operate in parallel.

The result is a repartitioning of the tasks in a typical base-station-processing system. This task is neither trivial in itself nor trivial in its implications for the packet-processing-software team. Consequently IDT in July will provide an Advanced Mezzanine Card-profile reference design that will include a full, production-capable evaluation board with four Texas Instruments Himalaya DSPs and a latency-accurate simulator. The IDT 70K2000Z is available for sampling now, and production will begin in November. The price is approximately $125 (10,000).