Altos Targets Statistical Timing Models

Staff Reporter -- Electronic News, 7/3/2006

To develop new cell characterization tools for IC designers working on complex SoCs at 90nm, 65nm and 45nm process technologies Altos Design Automation Inc. has been formed with emphasis on the creation of statistical timing models.

The Santa Clara, Calif.-based company is introducing its first tool today, part of a toolset that Altos claims runs at least an order of magnitude faster than the current generation of in-house and/or commercial cell characterization tools.

Altos also said its tools aim to bring fully-automated vector generation capabilities to IC designers to alleviate the arduous manual setup requirements of many current tools.

The company is privately funded and was founded in January 2005 by former CadMOS executives Jim McCanny, CEO; Ken Tseng, CTO; Kevin Chou, VP of R&D.

The founders moved to Cadence when that company bought CadMOS in 2001. At Cadence, the team said it was involved in developing timing and signal integrity analysis technology.

“Characterization is at the cornerstone of the design flow, enabling every step from RTL synthesis through to electrical signoff,” McCanny said in a statement. “Designers at 90nm and below need a lot more library views than before to manage leakage, signal integrity, dynamic power consumption and yield.”

“However because current characterization flows take too long, designs are often taped out with old or inappropriate process, voltage, temperature corners. This results in slipped design schedules and a much higher risk of silicon failure. At 65nm and below, where statistical timing models are needed, the characterization bottleneck becomes even more acute,” he continued.

“We believe statistical static timing analysis (SSTA) will be essential for high yields at 65nm and 45nm. However, creation of statistical timing models is potentially a major barrier to SSTA adoption. There is a huge increase in the number of simulations required to accurately model systematic and random process variation,” Tseng said.

“At Altos, we've been able to speed up characterization by over an order of magnitude for both nominal and statistical models, essentially removing this roadblock and paving the pathway between DFM/DFY flows and design implementation,” he explained.

To create the optimal vector set and simulation conditions to maximize throughput and ensure full coverage of all logic states, Altos said it deploys a novel “inside view” approach to characterization where each cell is pre-analyzed. The company believes this is especially effective for modeling the impact of random process variation where each transistor within a cell can vary independently.

In addition, Altos said it has integrated its own Spice engine to further reduce the simulation overhead, although third party circuit simulators such as Spectre, Hspice or Eldo are also supported.

The company’s first product is Liberate, which Altos describes as a high-speed, fully-automated library characterizer for standard cells and I/Os that supports the creation of advanced current source models for timing (CCS and ECSM) and signal integrity (CCSN).

Liberate aims to deliver a significant reduction in characterization costs and turnaround time – as much as ten times run time improvement -- coupled with improvements in ease of use and model quality, Altos said.

CEO McCanny said “Characterization has become increasingly challenging due to both the increase in the number of views and the complexity of the cells required to support low power, high yielding  nanometer designs. Liberate, because of its fast performance and the quality of its models, enables designers to get all the views they need to fully validate their design, thereby reducing the risk of silicon failure.”

Liberate uses the company’s “inside view” approach for characterization. Rather than the traditional black-box method, each circuit is pre-analyzed to determine the minimal required set of simulation vectors, the most optimal way to condition each simulation and initial bounds for constraint determination, Altos says.

By using automatic vector generation, Liberate avoids potential errors caused by manual or pseudo-manual vector creation where certain logic states can be overlooked, increasing the risk of silicon failure, which is especially helpful for complex cells such as state retention flops that deploy power gating techniques and sleep modes to reduce power consumption.

“New models such as CCSN for signal integrity require a new approach to characterization,” CTO Tseng noted. “The black-box approach that is widely used by many existing tools is no longer effective. By performing upfront circuit analysis to understand the internals of each cell, characterization time can be dramatically reduced and improved models can be created.”

Once the correct stimulus for each circuit is determined the simulations can be performed either by Altos’ built-in Spice engine or by a third party circuit simulator such as Spectre, Hspice or Eldo. Using the combination of Altos’ circuit analysis and the integrated simulator results in an order of magnitude improvement in characterization turnaround time and a highly-accurate cell model where every logic state is accounted for.

In addition to the traditional non-linear delay, power and signal integrity models, Liberate generates advanced current source timing models that are especially effective at modeling the impact of voltage drop on delay.

“Advanced current source timing models such as CCS and ECSM require careful selection of the sampling points. Select too many points and the library data size explodes, select too few and you lose accuracy. Liberate is able to capture the correct number of samples via on the fly validation and dynamically adjusting the sample range to minimize size while ensuring accuracy,” concluded engineering VP Chou.

Liberate is available now with U.S. pricing starting at $95,000 for a one year license.