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Packet switching comes to backplanes
By Ron Wilson, Executive Editor -- EDN, 7/7/2006
By looking at switching equipment, you’d never know that the trend in the communications and networking world is toward TCP/IP (Transfer Control Protocol/Internet Protocol). Once packetized data enters a line card and passes through a traffic-manager ASIC or NPU (network-processing unit), it almost universally emerges onto the backplane as fixed-length cells, rather than as packets. Such is the lingering legacy of ATM (asynchronous-transfer mode), or, if you have a longer memory, of ISDN (Integrated Services Digital Network).
Serious inefficiencies occur in the communication between variable-length packets and fixed-length cells, however. Each cell must have a header. And, as the network schedules, prioritizes, and divides packets into cells, these headers, combined with the inability to fill all the cells, it can lose as much as 50% of the data bandwidth, according to Robert Sturgill, president and chief executive officer of start-up Enigma Semiconductor. Sturgill may be biased, however, because Enigma has just announced an alternative approach: a family of scheduling and switching chips that move variable-length packets across backplanes at the kinds of speeds today’s metropolitan-area-network edge routers and mutiservice switches demand.
Sturgill says that switching packets across the backplane poses formidable problems. You must concatenate packets with little dead time between them. Otherwise, the resulting efficiency is worse than for a cell-based switching system. And the shared-memory architectures for packet switching scale well only up to the limits of the memory chips for implementing those architectures.
With these problems in mind, Enigma developed a fabric manager (picture) employing an algorithm that relates to SONET (synchronous-optical-network) virtual concatenation. In this approach, “byte-aligned transmission,” nearly head-to-tail packets stream through a switching fabric. Combining this idea with an exhaustively tested on-the-fly scheduling algorithm and a lightweight packet header produces a system architecture that reaches 98% efficiency, according to the company’s simulations. Meanwhile, the new fabric attacks the problem of scalability by abandoning the shared-memory approach, instead employing full crossbar switches. Adding switch chips linearly expands the fabric’s bandwidth.
For implementation, Enigma’s designers employed a two-chip approach using TSMC’s 130-nm, low-voltage process. The first chip, the fabric-manager, resides on the line cards and connects to four SPI 4.2 streams to and from traffic managers or NPUs. The chip prioritizes packets according to quality-of-service request tags, attaches their headers, and concatenates them into an outgoing stream toward the fabric—or vice versa for traffic moving in the other direction. The proprietary prioritization scheme provides for eight classes of service. According to Enigma’s vice president of marketing, Ian Ferguson, the device can also dedicate some links to handle either switched-network traffic or video-over-Internet Protocol and similar payloads. The chip includes a significant amount of on-chip memory to eliminate the cost and space of using off-chip RAM on the line card.
To connecting the fabric manager to its fabric, Enigma employs the ABP (Advance Backplane) physical-layer technology from Rambus, allowing a speed of 12.5 Gbps per link between line cards and the backplane. The availability of a variety of codecs permits designers to choose a trade-off point for raw speed versus reliability.
The second chip, EN61xx crossbar switch, integrates as many as 36 ABP links per chip and can reach an aggregate throughput of 360 Gbps of nonblocking, full-duplex traffic. The devices will be available in a range of sizes and ABP link maximum speeds. The company expects to have both chips, the supporting system-level simulation, and the modeling tool available for sampling this month.
