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Fast read-channel IP challenges integration methodology
Design decisions: Developing a 2.8-Gbps read channel is one thing. Making it compatible with a standard-cell design flow is another.
By Ron Wilson, Executive Editor -- EDN, 8/22/2006
Infineon Technologies AG announced in early August what may be the fastest disk read-channel IP (intellectual property) core in the industry, at 2.6 Gbps. While the achievement is impressive in its own right and particularly significant for Hitachi, Infineon's key customer in the storage market, the design has implications well outside its narrow initial market.
First, the design represents a new data point in the continuing debate about whether high-performance analog circuits can continue to migrate into increasingly difficult processes. The read-channel core is an intensively mixed-signal design, implemented in 90-nm CMOS. Infineon's Dresden, Germany, facility and the compatible 90-nm process at UMC will be able to produce it.
The AFE (analog front end) on the design has been measured—in the lab—at up to 2.8 Gbps, according to Paolo Cocchiglia, Infineon's vice president of business development. That leaves some headroom above the maximum performance of the digital section of the PRML (partial-response, maximum-likelihood) channel. Clearly the problems known to bedevil 90-nm analog transistors did not stall Infineon's design team.
But raw speed was not the only criterion the AFE designers had to contend with. Infineon designed the core to serve three separate markets for Hitachi and other mass-storage vendors interested in using the design: the 1- to 1.5-in., low-power segment for handheld consumer electronics; the notebook segment; and the enterprise segment. Each of these segments falls on a different point along the power-versus-performance curve. The curve begins in the handheld space with extreme low-power measures—including reduced operating voltage and aggressive shutdown of idle circuits—combined with 300- to 400-Mbps throughput. It tops out in storage-server applications with full-bore, 2.6-Gbps throughput and the highest operating voltage.
Covering this range has numerous implications, according to Cocchiglia. Obviously, the AFE must deliver adequate bandwidth to meet the full range of bit rates. But less obviously, it must maintain adequate noise, jitter, and linearity specifications over that entire bandwidth, and over a considerable range of operating voltages. Moreover, the analog circuitry, like the digital blocks behind it, must support graceful power-down during standby modes.
Additionally, the AFE must offer nearly as much programmability as the digital section. Because the broad market will require the read channel to work with a number of quite different head/media combinations, the AFE must make such analog parameters as gain and filter corners register-programmable.
This demand for flexibility also influences the choice of feedback scheme for the modulator. Analog feedback can be higher in energy efficiency and lower in latency. But digital feedback is more easily configurable, offers a wider variety of control schemes, and migrates to other fabrication processes more easily. Cocchiglia declined to describe the modulator architecture in this design.
Further, the AFE must be bulletproof with regard to noise from surrounding digital circuits. To begin with, the analog blocks must reside right next to the high-speed signal-processing circuitry that makes up the rest of the read channel. Designers can deal with that in the design and layout of the core, which is delivered as a hard macro. However, in perhaps 80% of applications, the storage vendor will integrate the core into a disk-control SOC (system on chip) along with error correction, data management, and interface circuits, and possibly even positioning and device-control logic. In practice, Infineon engineers will undertake the integration job. But even for them, the task only becomes possible if the core exhibits very high noise immunity. In particular, that means the core designers must pay careful attention to supply and ground routing, according to Cocchiglia.
Another implication of reusability: the core must fit into a standard design flow. In Infineon's case this means a Magma-based flow using standard back-end tools. So although the AFE must be hand-crafted, the digital portion of the read channel—the digital portions of the data converters, the FIR (finite-impulse-response) filter, the Viterbi CoDec and whatever post-processing and write pre-emphasis circuits the customer requires—must be implemented in standard-cell methodology.
Ironically, this digital section turns out to be the performance limitation in the design, according to Cocchiglia. Infineon found that it was just possible to meet the performance requirements with a standard-cell digital design.
Performance represented a critical parameter in the design. The core had to offer enough raw speed to not only satisfy enterprise applications but also give SOC designers adequate headroom in the other market segments. When you put a core like this onto the inherently noisy substrate of an SOC, you are going to give up speed. "So far, we have only pursued integrated designs for desktop markets in the 1.8- to 2-Gbps range," Cocchiglia says. "That gives the integrators lots of headroom to work with. If we undertake an integrated SOC for the enterprise market, we will have to watch very carefully how much speed or jitter we are giving up during the integration process."
Looking down the road, Infineon will probably migrate the core to 65-nm technology to obtain even more speed. Beyond that, Cocchiglia says that iterative coding is on the horizon to replace PRML. In fact, iterative coding looks set to drive as much of a revolution in storage as PRML did when it swept away peak-detector read channels years ago. "Iterative coding has been used in satellite communications for years," Cocchiglia says, "but it has always been far too complex and required far too much power for use in storage applications. At 65 nm that may no longer be true. The higher performance available now may mean that we can use basically the same digital architecture we have today on the new coding scheme."
