Intel Shows 80-Core Test Chip

By Jessica Davis -- Electronic News, 9/26/2006

SAN FRANCISCO - Intel today provided a peek at a tera-scale research test chip with 80 cores that uses a mesh interconnect for on-chip communication.

CTO Justin Rattner announced the test chip during his keynote address at the Intel Developer Forum here and outlined two other breakthroughs that he believes will drive the future of tera-scale computing.

“We just got silicon back earlier this week,” Rattner said. “… It’s an order of magnitude better than anything available today.”

Intel said the device is the world’s first programmable teraFLOP (one trillion floating-point operations-per-second) processor. The device contains 80 simple cores and operates at 3.1GHz, and will allow Intel to test interconnect strategies for rapidly moving terabytes of data from core to core and between cores and memory.

Another breakthrough to speed communications between cores and memory comes in the form of a 20MByte SRAM die that is stacked directly underneath the processor chip.

“The chips have been bumped appropriately so that when they meet there are thousands of direct connections formed,” said Rattner. The design provides more than a terabyte per second of bandwidth between memory and the processor cores.

And Rattner also recounted the company’s recent hybrid silicon laser chip announcement. The breakthrough, created in collaboration with researchers at the University of California, Santa Barbara, makes it possible for anywhere from a dozen to hundreds of hybrid silicon lasers to be integrated with other silicon photonic components on a single chip.

The design uses a silicon-on-insulator (SoI) substrate, but during a question and answer session with the media, Rattner was quick to dismiss this chip’s use of SoI as a wholesale endorsement of the substrate by Intel, or any plan to use it for volume manufacturing. In a later manufacturing session, Intel Manufacturing VP Tom Franz said Intel had no plans to move to SoI.

Rattner said the expense of the hybrid silicon laser chip remained very high – about $100 per pin. 

“But this is a CMOS compatible approach, using facilities you’ve already paid for,” he said.