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DesignCon panel: 65-nm technology ready for mixed-signal designs; analog ICs, not so much

By Michael Santarini, Senior Editor -- EDN, 1/31/2007 12:13:00 AM

The day when engineers commonly implement analog ICs in 65-nm silicon may still be a decade away. But according to participants in a Tuesday panel at DesignCon 2007, 65-nm technology is proving its worth for analog-interface functions like physical layers for SERDES, PCIe, and Xaui.

During the panel, entitled "Life begins at 65—Especially for mixed signal," which Dataquest analyst Stephen Ohr moderated, silicon vendors, IP vendors, and noted analog-design specialists discussed the difficulties of implementing analog and mixed-signal functions in 65-nm silicon.

Boris Litinsky, senior staff engineer at Juniper Networks, said that 65 nm has many advantages in terms of cost and performance. In particular, he noted that 65-nm technology affords users twice as many gates to work with, that a 6T SRAM cell is 50% smaller than in 90-nm technology, and that a 1T cell is 35% smaller. Litinsky also noted that 65 nm provides designers with a 30% improvement in gate delay, a 50% improvement in active power reduction, and a 20% improvement in standby power reduction, compared with the 90-nm node.

Litinsky said that his group's devices incorporate a lot of high-speed SERDES (serializer/deserializer) functions and that Juniper tends to purchase these mixed-signal functions from IP vendors. "At 65 nm, we haven't done a huge amount of volume so far and we haven't seen any issues with third-party IP at the node," he said. "It doesn't mean there won't be any. I'd have to say for our limited usage at 65 nm, we're doing quite well. 65 nm allows us to really reduce power and offer better value to our customers."

Indeed, Joachim Kunkel, vice president and general manager of the IP group at Synopsys, said that his company is doing good business with its interface IP—including PCIe, SATA, and DDR2—at the 65-nm node. "We can only put all the work and all the effort into areas that are going to find their way into many chips," Kunkel said.

RF represents the next frontier for IP from Synopsys. "We started doing this with wireless USB," Kunkel said. "We have the WiMedia PHY analog front end that is working in TSMC 130 nm. Then we'll take it from there. It is still something we have to prove."

While panelists agreed that 65-nm technology is relatively well suited for mixed-signal design, they indicated that it is going to be a long time before it becomes a mainstream process for analog design.

The panelists and moderator all noted that today, engineers implement most analog designs in 0.5- to 0.25-micron processes. Unlike in the digital-IC business, pushing to new nodes is not a huge priority in the analog space, said Robert Dobkin, vice president of engineering and chief technical officer at Linear Technology.

"Digital functionality is increased with the number of transistors and speed, so pushing to smaller sizes is necessary to increase productivity in the digital world," he said. "Our functionality is not necessarily based on transistor size but may be based on device parameters and circuit parameters, so getting improved performance or productivity doesn't necessarily mean more or smaller transistors, because the analog functionality is a function of the design."

That said, panelist Dieter Draxelmayer, analog technologies fellow at Infineon Technologies and Bob Pease, staff scientist at National Semiconductor, noted that some analog designs are making their way to advanced nodes already. Draxelmayer claimed that an upcoming show will include several papers in which designers discuss implementing ADCs in 90-nm processes. Meanwhile, the ever-colorful Pease noted that his company has created an analog device in 65 nm.

Earlier in the panel, Pease provided a bit of a diversion for attendees. Using an old-fashioned overhead projector, he displayed several old-school, hand-written foils describing how National engineers ran Spice models on commercial simulators that indicated a particular design, the LA1291, couldn't be manufactured to their specifications. Then, brandishing a rather large breadboard, Pease said, "I did it on a breadboard. You can look at it but don't pet it too damn hard. Spice just lies—you gotta watch out for Spice."

When later asked if National had used Spice models when working on the 65-nm analog device he had mentioned, Pease responded, "I don't know, it wasn't mine."