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Panelists discuss emerging dc/dc-conversion challenges

By Paul Rako, Technical Editor -- EDN, 1/31/2007 7:31:00 AM

Engineers face a growing dc/dc-conversion challenge in both notebook and server designs, and vendors could do more to help the situation by delivering more complete characterization of dc/dc-converter modules, according to participants in a panel Tuesday at DesignCon.

Chaired by Istvan Novak, a signal integrity senior staff engineer at Sun Microsystems, the panel featured Don Nguyen, power technologist for Intel and Shaun Harris, power system architect at Hewlett-Packard.

Nguyen led the session off with a presentation focused on laptop design. Higher switching frequencies can reduce the cost and size of inductors and capacitors, he pointed out, but with a penalty in efficiency. An added challenge to designing efficient converters for laptops is the wide input-voltage range coming from the wall supply. If the input is 9 to 20V, the system incurs an efficiency penalty compared with a system that has the dc/dc converters operating from 9 to 12.5V, which is the range of the battery pack.

Nguyen presented Intel data that showed how chips that integrate the drivers and MOSFETs improve efficiency by several percentage points. Such chips reduce the capacitance that the driver has to supply and more importantly reduce the inductance of the gate-drive net so that faster rise times can be achieved. As laptop dc/dc converters approach 750-kHz switching frequencies, fast rise times become a critical aspect of efficiency. The reduced PCB footprint of integrated driver-MOSFETs represents an additional benefit for laptop designers. Nguyen mentioned that some engineers have dubbed these integrated "driver FETs" as "DrFETs" (pronounced "doctor FETs)."

Harris focused on the challenges for engineers working on server racks that burn as much as 10 kW of power. Such servers often have 200 different dc voltage rails, he pointed out. With so many rails, reliability suffers because the failure of any single voltage rail will cause the entire server to shut down. Moreover, adding redundancy can quickly lead to a situation of diminishing returns—as this implies 400 voltage rails in the server and significant added complexity, Harris said.

In this regard, Harris came down firmly in favor of digital power techniques such as PMBus and the use of digital monitoring to anticipate failures. If a system can inspect itself for thermal or other problems, the server's workload can conceivably be transferred to a different rack while diagnostic and repair efforts proceed on the problem rack. Harris reported that power FETs used in both high-side and low-side switches have the highest incidence of failure in servers.

Novak finished up the presentations by pointing out that manufacturers of dc/dc converters have no insight into the feedback circuit, as well as the load, that their converters will face in the final application. It's therefore imperative that manufacturers characterize converters fully and that this data be shared with customers, Novak said. For example, manufacturers rarely specify the phenomenon of ringing, even though it can interfere with system clocks and cause other problems.

A 3-D chart of impedance over load and frequency would go a long way toward making the designer's job easier, Novak said. He presented several gain-phase and impedance plots of various converters. Some had a nice stable profile everywhere; others exhibited peaks and valleys that would make the system design difficult at best.

Novak cited the low bandwidths of some converters as a concern. Low control-loop bandwidth makes for sluggish but predictable response with plenty of phase margin. If vendors would provide the option for high-bandwidth converters, then the size of the bulk output capacitance could be reduced because the converter would respond in a timely fashion.

Another complaint regarded digital-loop-converter blocks. Novak noted that digital control loops employ nonlinear techniques to achieve good transient noise response. This makes characterizing the converters in the frequency domain problematic because that analysis is based on linear math. Instead, the characterization should be done in the time domain. In analog loops, a designer could always measure input voltage, output voltage, and load current over frequency. Doing the characterization for digital loops requires the measurement of input voltage, output voltage, and load current, and instead of frequency, the variable is the rise time of the time-domain excitation.

Also, manufacturers must characterize a complete set of changes in load-step magnitudes in order to fully understand how the digital control loop will behave. Novak called for better models of converters, especially digital ones. He also requested a standardized interface to those models. In addition, he called for better characterization of converter drive-frequency ringing.

After the presentations, audience members asked several questions. One perceptive questioner maintained that a frequency-domain plot from a network analyzer would show a large anomaly at the switching frequency of the converter. Engineers might misinterpret this as a problem. Novak agreed that the anomaly would occur, but noted that it would appear as a very sharp spike. Engineers could simply choose not to gather data at that frequency or to ignore the spike in a plot. True problems in a converter's gain-phase or impedance plots, by contrast, would appear as wider dips and peaks in the response, he said.

One final note of caution for engineers: When Harris referred to "digital power," he was talking about digitally reporting system health. When Novak used the term, he was referring to dc/dc converters that use a digital control loop comprised of a DSP or state machine. To avoid confusion, engineers should make sure to clarify the context in which they hear the term; it can mean widely divergent things.