IBM doubles microprocessor performance with embedded DRAM technology

By Ann Steffora Mutschler -- Electronic News, 2/14/2007

At the International Solid State Circuits Conference being held in San Francisco this week, IBM Corp. is announcing what it says is a major step forward in solving the multi-core bottleneck; detailing on-chip memory technology that it claims has the fastest access times ever recorded for embedded DRAM.

IBM says the technology effectively doubles microprocessor performance beyond what classical scaling alone can achieve and vastly improves microprocessor performance in multi-core designs and for the movement of graphics in gaming, networking, and other image intensive, multi-media applications.

Designed with its silicon-on-insulator (SOI) technology, IBM says it has demonstrated record-setting performance, at dramatically reduced power when compared to conventional SRAM.

The company also says this embedded DRAM technology will be a key feature of its 45-nm microprocessor roadmap and become available in IBM’s systems and OEM technology beginning in 2008.

The technology, designed in stress-enabled 65-nm SOI using deep trench, is meant to improve on-processor memory performance in about one-third the space with one-fifth the standby power of conventional SRAM.

Dr. Subramanian Iyer, distinguished engineer and director of 45-nm technology development at IBM explained in a statement, “With this breakthrough solution to the processor/memory gap, IBM is effectively doubling microprocessor performance beyond what classical scaling alone can achieve.”

“As semiconductor components have reached the atomic scale, design innovation at the chip-level has replaced materials science as a key factor in continuing Moore’s Law. Today’s announcement further demonstrates IBM’s leadership in this critical area of microprocessor design innovation,” Iyer added.

Specifications of the eDRAM include: 0.126 square millimeter cell size, a one volt power supply, 98.7 percent availability, 1K RowX16 Col X146 (2Mb) tiling, 76 mW AC power, 42 mW stand-by keep alive power, 2-nanosecond random cycle time and 1.5-nanosecond latency.