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IBM to roll out 45-nm immersion process by end of year
By Ed Sperling -- Electronic News, 2/23/2007
IBM and its growing list of silicon manufacturing partners will begin rolling out immersion lithography for 45-nanometer processes in Q4, a technology that IBM believes will carry silicon manufacturing to 22-nanometers and possibly beyond.
The announcement has a litany of ramifications because of the long list of partners now working with IBM. AMD, for one, will remain toe-to-toe with Intel on the Moore’s Law road map for x86 processors. In addition, IBM partners Freescale, Toshiba, Sony, Infineon and Samsung will remain on the cutting edge of the road map for a variety of other semiconductors. And IBM manufacturing partners Samsung and Chartered Semiconductor will remain on the forefront of manufacturing processes at the most advanced and increasingly expensive nodes.
George Gomba, IBM’s director of lithography technology development, told Electronic News that in the future, a viable semiconductor strategy requires collaborative innovation because of the dramatic increase in complexity and cost. Immersion is just one step in that direction, but Gomba said it is a necessary one and something Intel will have to contend with at some point. Also coming in the future are such techniques as double patterning to increase chip density, as well as a variety of new materials.
“At 22-nanometers, we will need a very aggressive resolution strategy, which will include predictive modeling and design for manufacturing,” Gomba said. “Immersion is the pathway there. It enables high numerical aperture imaging and tolerance control.”
All of these techniques will send the price of chip photomasks—the blueprint for manufacturing the chips—far beyond the $1 million average cost at 90 nanometers. Mistakes will cost many millions of dollars in time and materials. They also will cost several months of development time, which generally means a lost market opportunity for companies that don’t get it right on the first try. Gomba said IBM plans to couple predictive modeling with deep computing to solve that problem—a process that will involve partners in the EDA space, as well as exposure tools suppliers.
While TSMC and UMC have said they are working on immersion, only IBM and its partners have announced an actual commercial implementation date. Intel will roll out 45nm chips later this year, and is expected to adopt immersion at 32nm.
Immersion uses water a medium between the lens and the wafer to boost refraction. The technology has been under serious development for at least several years by most foundries, with future research expected to boost refraction through mediums other than water.
