News and New Products

Synopsys tools tackle verification progress

By Michael Santarini, Senior Editor -- EDN, 3/7/2007

When have you done enough verification? That’s the age-old question Synopsys is attempting to answer with three new additions to its IC-verification lineup. In 2005, Synopsys and ARM introduced Verification Methodology Manual for SystemVerilog, by Janick Bergeron, Eduard Cerny, Alan Hunter, and Andrew Nightingale (ISBN 978-0-387-25538-5, Springer, 2006). The book outlines how to introduce assertions into advanced IC-verification-tool flows. Now, the company is taking that knowledge a step further by incorporating tools that help verification teams create and monitor verification methodologies and more easily incorporate assertion-based verification into flows.

The three new VMM (Verification Methodology Manual) applications, which hook to the company’s VCS (Verilog Compiled Simulator) environment are VMM Planner, VMM Applications, and VMM Automation. “One of the biggest challenges in verification is to determine how much progress has been made, being able to measure that progress, and, based on that measurement, predict how close verification engineers are to closure while guaranteeing quality for the design they are verifying,” says Swami Venkat, director of product marketing for RTL (register-transfer-level) verification at Synopsys.

Traditionally, design teams use a spreadsheet to create verification plans and write scripts to extract data from nonmachine-executable simulation log files to monitor verification progress. Traditionally, this method has been difficult to maintain, and it relies on every design-team member’s diligence. So, Synopsys has figured out a way to automatically tie in much of that verification-data monitoring to its verification environment with VMM Planner, which allows verification managers to capture, track, and measure verification progress. “VMM makes planning more definable, and the data being used for planning is machine-executable,” says Venkat. The tool captures data from verification tools using spreadsheet formats and then rolls up a variety of verification results, such as code and functional coverage, formal and dynamic assertions, and test pass/fail data, into an annotated plan. The tool hierarchically organizes verification projects and allows users to track source files; code, assertion, and state-machine coverage; lines of code that have changed; and pass/fail data and bug tracking. “Depending on what a team feels is important for it to track, it can define that factor as a metric, and VMM Planner will allow them to track progress against that metric,” says Venkat.

With VMM Applications, Synopsys attempts to help designers more easily and more quickly create testbenches. The company has built macroblocks of high-level test functions from basic SystemVerilog elements in its VMM standard library. The company is rolling out the first version of VMM Applications with macroblocks for the register-abstraction layer to help verification engineers verify chip registers with tests that the tool automatically generates. The tool also has macros for the abstraction layer to help users configure VMM testbenches to mixed simulation environments, hardware-assisted verification environments, or both. VMM Applications users will also be able to create reusable verification subsystems, and the tool features a memory-allocation manager that checks designs for memory-buffer content and address bugs.

VMM Automation features the VMM SystemC and VMM Compliance Checker applications. VMM SystemC acts as a higher performance interface between VMM SystemVerilog testbenches and SystemC reference models, and VMM Compliance Checker checks that verification environments comply with the rules and guidelines of Verification Methodology Manual for SystemVerilog, which helps verification teams further increase their chances of speeding through verification. VMM Planner and VMM Applications are available now in beta, and Synopsys hopes to have VMM Automation tools ready over the next 12 to 24 months. The tools are free with the VCS Simulator or the Pioneer testbench tools.