News and New Products

Calypto fields RTL-clock-gating tool

By Michael Santarini, Senior Editor -- EDN, 3/27/2007

EDA start-up Calypto Inc has broadened its product portfolio beyond system-to-RTL (register-transfer-level) functional-verification tools with the introduction of an automated clock-gating tool for low-power-IC design. The PowerPro CG (clock-gating) tool complements the company’s SLEC (sequential-equivalence checker) CG, RTL, and other functional-analysis tools. PowerPro CG targets helping design engineers create low-power designs. The company claims that, using the tool, beta customers that were previously performing manual clock gating on their designs further reduced dynamic-power consumption by as much as 60%.

Tom Sandoval, chief executive officer of Calypto, says that one of the most popular ways that engineering teams reduce power consumption in IC designs is to gate clocks, but designers traditionally do most of the gating late in the design process at the gate level during layout; as a result, they must manually perform this task. With PowerPro CG, Calypto hopes to change that situation. The analysis-driven PowerPro CG allows designers to reduce dynamic power without impacting leakage power, area, or timing, according to Sandoval.

Designers will use the PowerPro CG with logic synthesis. Designers run the RTL versions of their designs in synthesizable Verilog or VHDL through synthesis to get a power figure. They then feed the raw RTL, an SDC (Synopsys Design Constraint) timing file, a SAIF (Switching Activity Interchange Format) file, and a Liberty Synopsys cell-library file to the PowerPro CG. The tool analyzes the RTL for clocks that designers can gate for further power savings. Users can select which clocks they want to the tool to gate and select critical paths they don’t want the tool to gate. The tool then analyzes the RTL and generates power-optimized RTL for the selected clocks. Users can then run SLEC CG to ensure that the power-optimized version of the RTL is functionally the same as the original RTL. Users can then run the power optimized RTL through logic synthesis.

The tool performs power optimization with no impact on timing, and, in most cases, the optimization reduces the overall die area required for the design. The tool takes advantage of the company’s SLEC sequential-analysis engine, finding opportunities to reduce power that manual inspection misses. “If engineers spend enough time inspecting RTL and analyzing how it works sequentially, they can come up with these same transforms,” says Sandoval. “But that task would be very difficult.” He notes that, for efficient clock gating, a tool or an engineer must consider which logic to gate and for how long and then must consider the trade-off of gating versus area or performance. “PowerPro optimization typically finds hidden opportunities for gating and opportunities to gate more obvious clocks for a longer period of time,” says Sandoval. PowerPro CG runs under Linux and sells for $295,000 for an annual subscription.