For nearly two decades, analyst Gary Smith has been a fixture in the EDA industry—advocating new tool flows and methodologies as the silicon times have changed. Late last year, Gartner Dataquest closed Smith's EDA-analyst group, but the former LSI Logic IC-design-flow methodologist and 25-year semiconductor veteran has started his own analyst company, GarySmithEDA. EDN recently asked his opinions on the state of the design business.

What has been the biggest change in the chip business since you started as an analyst?

The biggest change has been the move from component suppliers to system-IC vendors. That change is affecting all of the electronics market. Basically, ICs were always components. You put them together on a PCB [printed-circuit-board] to make systems. But, as we got more and more gates available to us, what we saw was a group of semiconductor vendors that moved out of the component-based market into the subsystem or even system market. They were actually doing the systems design.

You mean rather than doing a system on a board, they were doing an SOC (system on chip)?

Yeah, and because it was now on-chip, the semiconductor guys were doing it, not the OEMs. Probably the best example is TI's OMAP [Open Multimedia Applications Platform] for the handheld market. Suddenly, we see the IC vendors determining system architectures. It's been a big, important shift. We still have a lot of component vendors, but the leading guys are system-IC vendors.

What are the hot IC-design-related topics this year?

Software, software, software, and then DFM [design for manufacturing] and the move to an ESL [electronic-system-level]-driven verification methodology. But software's the biggest problem, and it needs to be solved. If anything slows down the industry, it is going to be a lack of embedded-software infrastructure for parallel processing. To solve the power problem, which started a few years ago, we started going to slower designs with multiple processors onboard. And, as we started getting more gates to work with, we started adding more processors to products like cell-phone designs. We're walking away from von Neumann architecture. Unfortunately, the software architecture is based on the von Neumann community's using C as a language, and it is all sequential. We've been trying to solve the parallel-[computing] problem since 1985, but the semiconductor vendors are at a point where they say "we've got to do it." Semiconductor vendors want to keep adding more processor cores—moving from four to eight to 16 to 1000—to their silicon, but the software guys are saying "I don't know why we can't program it." We are reaching this cliff that, if we don't solve the problem, the semiconductor industry is in trouble.

I saw this neat design the other day; it had 175 processors. One was working its ass off, and the other 174 were keeping it warm. DARPA [Defense Advanced Research Products Agency] recently funded Sun Microsystems, AMD, and Cray to come up with a concurrent-design language, and there is serious work going on at IBM, Intel, and ARM. The ITRS [International Technology Roadmap for Semiconductor] is also on the case, so now folks are starting to realize this is a big deal.

The 130- and the 90-nm nodes both required retoolings. When do you think the next retooling will occur?

It happens every two nodes. We are now beginning the move from 65- and 45-nm tools to 32- and 22-nm tools. The 65-nm node wasn't nearly as hard as we expected. Typically, the first of the two processes [when there's been a significant change in IC manufacturing, such as the introduction of copper at 130 nm] is the most difficult, and that's when the power users [designers of the most advanced chips] need new tools. Unfortunately, it usually takes the EDA industry a bit of time to catch up and offer tools for new problems.

Will high-k dielectric have a big impact and force a retooling?

It will have an impact. They are now talking about new materials and a two-mask process; there are going to be a lot of changes that may cause ripples in the design flow. We are starting to do 45-nm designs now. We should have had 45-nm tools in September, but we don't seem to have them yet.

What tools or skills will the retooling require?

On the silicon end, it requires model-based DFM; on the complexity side, it requires a solid ESL flow.

Who are the up-and-comers in the EDA business? Are there any hot start-ups on the horizon?

In DFM, keep an eye on Clear Shape and Blaze DFM. In ESL, keep your eye on Co Ware, Mentor, and The Mathworks. For the start-ups, Imperas stands out. It is one of the companies that is trying to come up with a language for parallel processing. There are a few others, but I still haven't met with them yet to see what they are really doing.