News and New Products

SST introduces hybrid NAND/NOR All-In-OneMemory

By Michael Santarini, Senior Editor -- EDN, 4/5/2007

Known primarily for its NOR-memory technology, SST (Silicon Storage Technology) is now adding to its portfolio the All-In-OneMemory device, which mixes NAND, NOR, RAM, and a memory controller in one system-in-package offering. The All-In-OneMemory will go head-to-head in the market with a slew of other mixed-memory code- and data-storage devices, such as Samsung’s OneNAND, SanDisk’s mDoC, and other devices vying for the system-memory slot in the high-end-handheld-device market.

SST expects to introduce the first silicon in the second half of the year and has not yet revealed the densities or nitty-gritty details of its new devices. Frank Lin, vice president of application-specific-controller products at SST, says, however, that each of the new devices in the family will feature a NOR and a NAND that an SST-built memory controller manages. The controller seemingly is the key innovation of the All-In-OneMemory because it decides which type of memory is best for a task and communicates tasks to the off-chip host CPU through a RAM bus. The controller includes embedded SuperFlash NOR blocks for boot code, a flash-file system for NAND-flash management, and a cache-memory controller for pseudo NOR that emulates high-density NOR flash.

“The All-In-OneMemory puts the benefits of NOR and the benefits of NAND into one subsystem,” says Lin. “We’ve added a controller to the subsystem, which eliminates the limitations of the NOR and the limitations of the NAND. We now provide a unified storage system for both data and code, and we offer advanced security features because of the controller.” The new system features as much as 8 bits of random ECC (error-correction code) and cache controller to handle demand paging and reduces the overall RAM requirements for designs.

“We are removing all the hardware and software requirements, like virtual paging, swap in, and swap out, from the host CPU for regular memory management, and we also removed the flash-file system and the ECC hardware for the NAND controller from the host controller,” he says. “The memory controller also optimizes the use of the NAND and NOR memories.”

All-In-OneMemory’s memory map, the host CPU, will interface with four random-access blocks and one sequential-access block through a single bus. The random-access blocks consist of a memory-controller-embedded SuperFlash NOR block for instant-on boot-up of the system, a high-speed pseudo-NOR on a separate NAND for executing time-critical code and data, a pseudo NOR on the NAND for code and data storage, and a RAM block for working code and data and pseudo-NOR caching. The sequential-access block comprises an ATA data-storage block on the NAND for non-XIP (execute-in-place) code and data. SST currently has working silicon for the device and expects to have the device ready in volume in the second half of this year.