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IBM details 3-D chip stacking breakthrough
By Ann Steffora Mutschler, Senior Editor -- Electronic News, 4/12/2007
In its quest for new materials and architectures to extend Moore’s Law, Armonk, N.Y.-based technology giant IBM today detailed what it is calling a breakthrough in chip-stacking manufacturing technology that paves the way for three-dimensional (3-D) chips that will extend Moore’s Law beyond expected limits.
The technology is called “through-silicon vias,” and is meant to allow different chip components to be packaged closer together for faster, smaller and lower-power systems.
IBM said this breakthrough allows the move from horizontal 2-D chip layouts to 3-D chip stacking, which takes chips and memory devices which traditionally sit side-by-side on a silicon wafer and stacks them on top of one another, resulting in a compact sandwich of components aimed at reducing the size of the overall chip package and boosting data speed between functions on the chip.
Lisa Su, VP of semiconductor R&D at IBM noted that the breakthrough is a result of more than a decade of pioneering research and allows the move to 3-D chips from the 'lab to the fab' across a range of applications.
IBM said its method eliminates the need for long-metal wires that connect today’s 2-D chips, instead relying on through-silicon vias, which are essentially vertical connections etched through the silicon wafer and filled with metal, and allow multiple chips to be stacked together, allowing greater amounts of information to be passed between the chips.
Further, the technique shortens the distance information on a chip needs to travel by 1000 times, and allows for the addition of up to 100 times more channels, or pathways, for that information to flow compared to 2-D chips, the company explained.
IBM said it is already running chips that use the through-silicon via technology in its manufacturing line and will begin making sample chips using this method available to customers in the second half of the year, with production in 2008.
The first application of this technology is expected to be in wireless communications chips for use in power amplifiers for wireless LAN and cellular applications.
IBM will also apply the 3-D technology to a wide range of chips, including those running now in its high-performance servers and supercomputers that power the world’s business, government and scientific efforts.
In particular, IBM noted that it is applying the technique in wireless communications chips, Power processors, Blue Gene supercomputer chips, and in high-bandwidth memory applications.
Specifically in the wireless communications realm, IBM said it is using through-silicon via technology to improve power efficiency in silicon-germanium based wireless products up to 40 percent, in order to lead to longer battery life. The technology replaces the wire bonds that are less efficient at transferring signals off of the chip.
Next, in its Power processors, IBM noted that as the number of processor cores on a chip increases, one of the limitations in performance is uniform power delivery to all parts of the chip. This new technique puts the power closer to the cores and allows each core to have ample access to that power, increasing processor speed while reducing power consumption up to 20 percent.
Further, in the Blue Gene supercomputing and memory array areas, Big Blue noted that the most advanced version of 3-D chip stacking will allow high-performance chips to be stacked on top of each other, for example processor-on-processor or memory-on-processor. IBM also said it is developing this advanced technology by converting the chip that currently powers the fastest computer in the world, the IBM Blue Gene supercomputer, into a 3-D stacked chip. The company is also using 3-D technology to change the way memory communicates with a microprocessor – by significantly enhancing the data flow between microprocessor and memory to allow a new generation of supercomputers. A prototype SRAM design using 3-D stacking technology is being fabricated in IBM's 300-mm production line using 65-nm-node technology.
IBM reminded it has been researching 3-D stacking technology for more than a decade at the IBM T.J. Watson Research Center and now at its labs around the world. The Defense Advanced Research Projects Agency (DARPA) has supported IBM in the development of tools and techniques for extending chips to the third dimension, with the aim of driving better performance and new applications of chip technologies, the company added.
Other recent chip technology advances from IBM include its announcement last month of a prototype optical transceiver chipset capable of reaching speeds at least eight-times faster than optical components available today.
In February, IBM revealed an on-chip memory technology that contains what it says is the fastest access times ever recorded in embedded dynamic random access memory. In January, IBM announced “high-k metal gate,” which substitutes a new material into a critical portion of the transistor that controls its primary on/off switching function. The material provides superior electrical properties, while allowing the size of the transistor to be shrunk beyond limits being reached today. Finally, In December, IBM announced its first 45-nm chips using immersion lithography and ultra-low-K interconnect dielectrics.
