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TSMC talks details on the meaning of 45-nm CMOS

Company strives, with some success, to make the 65- to 45-nm transition transparent to chip designers, EDA tools.

By Ron Wilson, Executive Editor -- EDN, 4/18/2007

Coincident with its announcement of its 45-nm technology platform last week, TSMC has begun to discuss the implications of the new process for chip-design teams. According to the company, some designers will find valid reasons to choose 45 nm, and the transition for many designers will not be difficult. But it won't be trivial.

"The transition from 65 nm to 45 nm for most design teams should be fairly smooth," says Jack Sun, TSMC's vice president of research and development. "These two processes represent pretty much the same solutions."

This appears to be true from the perspective of both a process engineer and a design team. On the process side, the 45-nm platform presents only two major changes compared with 65 nm, according to TSMC. The 45-nm process will introduce the use of immersion lithography for critical layers, and it will move to a lower-k porous material for inter-metal dielectric.

Beneath that visible surface lies a network of intensive engineering, according to Sun. In order to scale process geometries without actually going backward in either performance or reliability, TSMC has pushed the use of strain engineering further, and the company has turned to new techniques to deal with the decreasing noise margins. New effects have appeared, such as the temperature-inversion effect, in which, because threshold voltage can increase with decreasing temperature, the worst-case delay for a circuit may actually be at the low-temperature corner rather than the high-temperature one.

TSMC has worked to keep new issues encapsulated either within process engineering, or, if that is not possible, within library development, so that neither EDA tools nor chip-design teams will have to deal with them directly, Sun says. Sometimes this works, and sometimes it does not.

The new dielectric material is a case of relative success. The material presents several challenges, according to Sun. It is much more fragile than previous low-k materials, which has necessitated design-rule changes to prevent the design of physically vulnerable structures. Typically, the low-k material will be used at lower layers, in conjunction with conventional glass at higher layers. Greater porosity means a greater threat of contamination, and hence a greater threat of increased effective k or even of dielectric failure. TSMC has countered these threats with more work on sealing-layer technology. This in turn reduces the effective cross-section of conductors, resulting in more design-rule changes. But the net effect is relatively invisible to chip designers.

In the case of increasing strain on the transistor channels, Sun says that TSMC has been largely successful in making the change transparent. The design team simply sees faster transistors. At a more detailed level, the increasing reliance on strain-inducing cap layers means that transistor performance is more dependent than ever on the geometry of nearby isolation trenches and etch-stop layer features. But these dependencies have been limited to a range that confines them within a single cell in most cases, so only cell designers need to really work with this source of pattern-dependent variation.

SRAM offers a less felicitous example. Sun says that despite faster underlying technology, there is no getting around the fact that SRAM cells at 45 nm have reduced voltage margins. TSMC has chosen to go with relatively conventional six-transistor SRAM and eight-transistor dual-port cells. "But with the reduced supply voltage," Sun warns, "designers must worry about IR drop and switching noise. In some cases we require that the rails be decoupled from the logic supplies. And in some cases arrays will have to be subdivided to keep the voltage margin under control."

In this and other areas, Sun claims, 45 nm will potentially offer greater speed than 65 nm. "The core transistor is faster," he says. "But that can be misleading. You have to use proper techniques to make that raw speed useful in a design."

Analog, not surprisingly, is another area of concern. But it may be a surprise that TSMC is confident about analog designs in the technology. "Using thick-oxide transistors and using the proper discipline for isolation techniques should give good results on analog circuits," Sun says. Similarly for RF, the raw speed of core transistors offers a potential advantage for designers. But the high leakage current and 0.9 to 1.1V core operating voltages in the process will impose serious challenges on RF designers.

In summary, Sun suggests that high-volume applications that can take advantage of the platform's density—either to reduce die area or to integrate analog and RF functionality—can clearly benefit from the 45-nm process. But the time is gone when a process migration automatically meant both greater density and higher performance without substantial architectural or circuit changes. You can get more performance, but it won't come easy.