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ChipVision’s Orinoco II generates RTL for low-power design

By Michael Santarini, Senior Editor -- EDN, 5/14/2007

Privately held EDA company ChipVision has extended the feature set of its Orinoco ESL IC-architecture-estimation tool so that it now has both design- and power-estimation capabilities. Previously, the tool boasted features only for analyzing the power consumption of ICs at the ESL (electronic-system level). Orinoco II can now help designers generate low-power RTL (register-transfer-level) code.

Until now, a lack of front-end power tools has forced design teams to deal with low-power design mainly during the gate level and physical-design steps, according to company President Thomas Blaesi. At that point, designers can make only a limited amount of adjustments to their designs to lower their designs’ power. The earlier you address power in your design flow, the more effectively you can create a design for low power that doesn’t require a lot of low-power adjustments later in the flow. “Most industry experts agree that the best method for effective power reduction is at the system level,” he says. “Selecting the correct architecture can make a huge impact on power savings—roughly 80% of power savings can be gained by creating a good architecture.”

To help engineers gain that advantage, the company has created new technology for Orinoco that allows system and RTL designers to interactively optimize area, power, and timing constraints to create RTL code. “We’ve created a technology that allows system and RTL designers to execute many architectural explorations and select the one with the lowest power consumption that still meets timing and area budgets,” says Blaesi.

Users feed the tool a C, C++, or SystemC version of their designs as well as IP (intellectual-property) blocks. They then feed the tool power constraints, such as clock-gating, clock-infrastructure, and power-supply information in either the UPF (Unified Power Format) or the CPF (Common Power Format). Users also feed the tools Synopsys .lib files, which, among other data, provides Orinoco II with transistor-leakage estimates.

You need to run the flow once per targeted process technology, says Blaesi. During that run, Orinoco II creates the power libraries that the tool uses. “The flow is automated, so customers can run it, or a ChipVision engineer can do it for them,” he says. Once you load the source code into the tool, the tool generates a tree-implementation profile or an activity profile for the design. The tool then performs an interactive synthesis that allows users to make power, timing, and area trade-offs. Users generate versions of the architecture and then select the one that best meets their power, timing, and area budgets. Once they choose an architecture, they use Orinoco II to generate RTL and create synthesizable Verilog. “At this stage, the RTL-design team can begin the engineering-change process and modify the code as desired,” says Blaesi. “We still believe the RTL is going to be the golden model for some time, so we make sure the RTL we generate is human-readable.”

Using the tool, beta customers have reduced power in their designs by 30 to 40%, reduced development times by a factor of 60, and realized a ninefold decrease in the amount of code necessary for achieving a low-power design. The company expects to release the tool this year but plans to demonstrate it at next month’s Design Automation Conference in San Diego. The company has not yet determined pricing for the tool.