News and New Products

What to expect at 45-nm

By Ed Sperling, Editor in Chief -- Electronic News, 5/11/2007

Electronic News/Electronic Business sat down to discuss bottlenecks and challenges at the 45-nm process node with Chuck Byers, director of worldwide brand management at TSMC; Ken Potts, VP of product marketing at Virage Logic; Rich Goldman, VP of strategic market development at Synopsys, and Mike Murray, general manager of the mixed signal IP business line at S3. What follows are excerpts of that conversation.

Q: What is the next bottleneck at 45-nm?
Potts: From an IP perspective, we’re facing challenges on a couple of vectors. One of them is process variation that comes in the form of atomistic effects. You’re dealing with gate oxides where you can count the number of atoms, so variance in that can change the circuit behavior. And then there are the complexities we’re dealing with, which raises the bar for validation requirements and making sure the silicon is going to be right the first time when customers are investing upwards of $75 million for a design start.
Murray: We think the variability issue is key. There’s a risk that we will design to cover all corner cases, and that way lose some of the advantages that scalability gives us by going to 45-nm in terms of power and performance. We need to collaborate—the IP vendors, the EDA vendors and the pure-play foundries—to ensure that we don’t lose the gains that the scalability gives us. We need more information on the devices in question. We need to use the EDA tools smartly and design methodologies to ensure that we retain the gains.
Goldman: If you have a gate oxide layer of four atoms and you lay down six atoms, you’re off by 50 percent. Variation is going to be a much greater issue at 45-nm. We need to be able to model that.
Byers: We’ve anticipated those challenges. With the rollout of 45-nm is that we had a relatively robust ecosystem up very early in the process development. What we have done is go with a model-based DFM process that takes all the information we have gathered to date, put it into a data kit, and moved that data up front in the process to the tool vendors. This is way early in the process to do this. The model-based DFM did not come into play until part way through the 65-nm rollout.

Q: But there wasn’t as much need for that at 65- as at 45-nm, right?
Byers: Yes, there is. Right the first time silicon is always needed. Some of these complexities are not new. Variants were new at 65-nm, but aren’t new at 45. The degree of difficulty has increased at 45, and will again at 32. Basically there are same issues, though. The first commercial 65 nanometers wafers were out at about this time last year. The amazing thing about those wafers was that it was right the first time. Even though the data was raw, it was still following this DFM paradigm. What has become even more critical is that we will have silicon at no time if you don’t have DFM factored into your design at 45-nm.

Q: Let’s go back to ecosystems. IBM has an ecosystem and TSMC has one. Can anyone remain an IDM at the bleeding edge of technology anymore?
Goldman: The trend that we’re seeing is the same one you noted in process development. It is so complex and expensive that most semiconductor vendors are finding they have to partner. That may mean going to a foundry like TSMC. There are examples like Texas Instruments. This company developed the first process. Now they’re saying they can’t do it on their own. They need to partner with a foundry. We all know the costs of not only process development, but also the cost of building fabs. These fabs are depreciating by millions of dollars a day. Getting the ecosystem in place early is important. Getting the fab up and running early is important, and the only way you can do that is through very close collaboration.
Murray: The vertical disintegration of the IDMs (integrated device manufacturers) is certainly happening. We launched our 65-nm data IP converter portfolio and we have traditional IDMs coming to us looking to license that IP. Some of these decisions were clearly ‘make’ decisions. Now they’re ‘make-buy’ decisions, or they’re being forced by their management into a ‘buy’ decision because it’s no longer economically feasible for them to make it in-house.
Potts: The fabless semi model is here to stay, providing innovation to the end customer. You have IDMs competing in those markets. When we look at what it takes to make an ecosystem successful, TSMC has to develop the process, we’ve got to do the IP, and we have to work closely with the end customer and the EDA guys to make all of this work. It’s not just TSMC’s process and our IP and tools from Synopsys. It is impossible to do it without close collaboration.
Goldman: The ecosystem is broader than that. We’re now collaborating with people like Nikon to take their scanner parameters, model them, and put them in with our tools so we can do things like predictive lithography. You need to be able to predict you can build a chip that is manufacturable. Where the tools are not doing that for you, you need fixes to get the yields up as high as possible.
Byers: There’s going to be another complication coming into this. This sounds very do-able. The first 45-nm node out will be low-power. It sounds like everyone has a handle on it. But the next node after that is going to be embedded DRAM, which has a whole new set of challenges. That will be the first quarter of 2008. Then mixed signal comes out. That’s the third node. What you’re seeing is the market is looking not just who has the latest and greatest. There is a great deal of integration expected and there is a great deal of specialization expected. A couple years ago the node would have been 0.13, and we would have all gotten together to talk about three chips and we would make it happen. That’s not the ball game anymore.

Q: Because of the incredible complexity and cost, are companies getting locked into individual ecosystems? It doesn’t sound like it’s feasible to have multiple foundry partners anymore.
Potts: Customers still want to source designs at multiple foundries, and we still see that. While there was some amount of divergence, it does look like there’s going to be some portability of design rules. There’s always some work in that, and that’s part of the challenge for us as an IP provider. But our goal is to enable our partners wherever they want to go.
Goldman: You still have the same issues in play at 45-nm. Competition comes for individual devices. You’re still looking at a mask set for a device design. What you’re competing for are those designs. Should you take a design to multiple designs, you’re looking at two different mask sets, which immediately increases your costs. Rarely do you find the same design in more than one foundry.

Q: The cost of working the bugs out of each of those designs at different nodes is higher, too, right?
Byers: Yes, but the ROI is higher, too. You’ve got a smaller footprint per die on a 12-inch wafer. You’re also picking up a good deal of functionality. At 45-nm, you’re dealing with a device that has twice the density.

Q: But is it worth doing two chips in the real world to provide multiple sourcing, or just one?
Byers: Right now the world is saying it’s just worth going with one. That’s been in play for awhile. Rarely does the same design go to more than one foundry.

Q: So is second sourcing dead?
Byers: No. There are more than one design per company.
Potts: And derivatives get run other places. At 45-nm, you’ve got to deal with process variation. IP developers have to tailor their IP to handle that or you’re going to end up with a quality result that’s worse than what you had at 65-nm. If you take the traditional sign-off approach, you have to go into the statistical domain and do things in your IP to account for the variance and monitor and adjust. Moving from foundry to foundry is not just a design rule issue. To the extent that you’ve got sophistication that customers can trust, they will do derivatives and other lines.
Goldman: To move from foundry to foundry is more complex. The mask costs are higher and the collaboration costs are much harder. It’s hard to collaborate with more fabs to create that ecosystem.

Q: But in the past, weren’t companies collaborating with multiple foundries?
Goldman: Yes, they were. But it’s getting more complex.
Murray: It takes much greater engineering effort for an IP provider to develop solutions for two different ecosystems. For us and TSMC, the window of opportunity for our customers is getting shorter, as well. They need to get their designs into the marketplace very quickly. When 45-nm comes on line, our customers want the IP to be ready online at the same time. That’s certainly a challenge. It means we need to get the technology information as early as possible from TSMC so we can start our data converter designs and get the silicon proven. That’s certainly a challenge.
Goldman: At 45-nm you’ll find virtually no chips that don’t have standard interfaces like PCI or USB. That IP has to be there. For it to be there, we have to work very early with companies like TSMC to prove it out. You also have to build it with very high quality so it’s test-able. And that all has to be done before we can get production chips through the fab.

Q: It looks the boundaries for EDA are changing. It’s now integrated in the back end of a design, which makes it harder to define what an EDA flow really is and who owns it. Is that correct?
Goldman: Yes, that’s absolutely correct. It has to start in the fab. You need a virtual fab with TCAD tools so you can model the process and optimize the fab using this process so you don’t have to do it all through building chips. That information then has to be brought up into the tools even before the process starts. That’s very early, and it requires close collaboration. When you start fabbing chips, you need a capability to test the chips and extract out all the process information, and then use that information to optimize the fab and then bring the process information back up into the tools.

Q: As IP players, does it make it easier or harder to figure out who to partner with?
Murray: It appears we are now heading toward two pure-play foundry consortia, which means there are less pure-play foundries bidding for consumer products. But the collaboration has to be deeper.
Goldman: It makes it much tougher to make choices, because the choices that you make are going to impact many more of your customers.
Potts: If you look at what we’re doing with TSMC at 45-nm, we feel this is what’s required to be successful. It’s getting in there, sharing the early information, and rolling that into the IP. When the process is ready to go, it has to be ready and silicon-validated. From a Virage standpoint, to collaborate effectively you have to have a deep relationship. We partner with those who have the capacity to share that information.

Q: From a foundry perspective, does it change your relationship with other companies?
Byers: It certainly makes the relationship tighter. All this activity we just enumerated took place at least six months ago for 45-nm. The collaboration is deeper, it is earlier, and it has moved from virtual to real.
Goldman: Our relationship with TSMC goes back much farther than six months. To do this intense collaboration, you need a longstanding relationship. We’re on reference flow 8.0, and we do one together every year. Every year we focus on a new capability—power, noise, yield. When 8.0 comes out, we’ll go right onto 9.0.