Renesas details next-gen CPU architecture

By Colleen Taylor, Contributing Editor -- Electronic News, 5/21/2007

Renesas Technology Corp. announced today at the In-Stat Microprocessor Forum that it is in the process of developing a new CPU architecture that it claims will offer "revolutionary enhancements" over previous-generation microcontrollers (MCUs) in code-efficiency, processing performance (MIPS/MHz), and power consumption.

Based on the new architecture, Renesas said it will offer two CPUs to address 16-bit and 32-bit markets, while maintaining compatibility with Renesas' existing MCUs. The architecture will provide upgrade paths for both markets, Renesas said.

Also, the architecture will have advances over the M16C and H8S 16-bit CPUs and R32C and H8SX 32-bit CPUs that Renesas Technology currently offers, while offering compatibility with the existing families in terms of CPU instruction sets, peripheral register sets and development tools.

It will combine the code efficiency of the M16C and R32C CPUs with the high-speed data processing of the H8S and H8SX CPUs, the company said, while boasting low power consumption and low noise. By employing this new architecture, Renesas said it aims to reduce code size by 30 percent and CPU power dissipation by 50 percent.

The project to develop the next-generation 16-bit and 32-bit CISC CPUs is currently underway, and the specifications of the new CPUs will be released in early 2008 with first devices with the new CPUs expected during Q2 2009 based on Renesas' 90-nm flash MCU process.