Intel stands behind high-k at 45-nm and below

By Colleen Taylor, Contributing Editor -- Electronic News, 5/22/2007

In continuing its steady pursuit of Moore's Law, market-leading MPU maker Intel Corp. is standing firm behind the use of high-k dielectric layers and metal oxide gates as the most efficient way to move toward ever-smaller process technologies.

"We really have entered a new era of process scaling," Mark Bohr, Intel senior fellow and director of process architecture and integration, said in his keynote at the Microprocessor Forum this morning. "Going forward, [processor design] is not just a matter of scaling dimensions; it's about using new structures and new materials."

The struggle to prevent power leakage within processors gets more crucial as processor design shrinks to smaller and smaller sizes. In order to continue reaping Moore's Law's promised benefits of scaling to smaller process technologies, Bohr said, new methods to prevent power leakage within transistors are crucial. Intel has chosen to prevent power leakage by changing the now-standard transistor design in two key ways between the silicon substrates and the low-resistance layer: replacing the silicon oxide substance with a hafnium-based high-k gate oxide substance; and replacing the polysilicon gate with a metal gate.

The use of high-k oxides and metal gates, Bohr said, increases transistor drive current by 20 percent, or the source drain leakage by more than a factor a five, and provides a reduction in gate oxide leakage by more than a factor of 10.

And this change in transistor design is "far more than just a laboratory device," Bohr said. "We have a 45-nm flow that meets reliability requirements and is manufacturable in high volume" using the new materials. Intel is on track to start shipments of MPUs made on 45-nm process technology in the second half of this year.

Standing firm in Intel's support of the superiority of high-k interconnects at smaller process technologies, Bohr dismissed IBM Corp.'s recent "Airgap processor" debut, which uses air vacuum interconnects to prevent leakage in lieu of silicon or high-k gate oxide layers.

"There are problems with Airgap technology that maybe were not fully disclosed [by IBM],” Bohr said, noting that the technology is potentially costly as it necessitates the use of an extra mask. In addition, he added that air vacuum interconnects may not be as reliable as dielectrics are in cooperating with transistors' copper wires.

"The cost and the reliability issues with interconnects are very important, and I don't think that air gaps are the solution to those. We are pursuing lower k versions of existing dielectrics -- I think this is more promising than air gap technologies," he concluded.