News and New Products

Lattice offers 90-nm, flash-based FPGA

By Michael Santarini, Senior Editor -- EDN, 5/29/2007

Lattice Semiconductor has announced its 90-nm, third-generation XP2 family of nonvolatile FPGAs, featuring preimplemented DSP blocks, along with twice the logic capacity and 25% greater performance than the previous generation. In 2005, the company introduced the 130-nm XP FPGAs, and, according to Gordon Hands, director of strategic marketing, Lattice has been diligently monitoring the device’s use and customer suggestions for the features of a follow-on product. The new XP2, Lattice’s first nonvolatile device in a 90-nm process, has better performance, higher capacity, and lower price per function than its predecessor, and it maintains reasonably low power for an FPGA.

The LatticeXP2 family comprises five members, with capacities ranging from 5000 to 40,000 four-input LUTs (look-up tables). The largest device is double the capacity of the largest device in the XP family. “We are using 90-nm technology, which is driving the cost of the device 50% lower price per function, and we spent a lot of time focusing on the power,” says Hands. Like the XP, the XP2 has a 1.2V operating voltage, but the new device has a 33% reduction in leakage power. Lattice stuck with 1.2V instead of going to 1V so that users could work with an operating voltage they are comfortable with and essentially swap out XPs with XP2s using the same power-supply circuitry.

With Xilinx recently jumping into the nonvolatile-FPGA market with its SIP (system-in-package) offering, Lattice now has yet another competitor in the market. But Hands claims that the single-chip, nonvolatile Lattice FPGAs offer better security, performance, capacity, and cost savings than SIP devices. With the single-chip XP2 device, Lattice employs FlexiFlash architecture. FlexiFlash preserves the benefits of the company’s previous flash-based devices: single chips with an instant-on feature. The new devices employ Flashback, a new approach to on-die user flash, which allows you to back up the contents of enhanced-bit-rate memories within the device.

With the XP, design teams can upgrade XP devices in the field without downtime for either the device or the system it runs. Flashback is essentially an on-chip backup; for example, if a power outage or another type of interruption occurs during a field upgrade, the device automatically reverts to and runs the previous version of the device program. The device also includes as much as 885 kbits of block memory in 18-kbit, dual-port blocks. Designers can also convert LUTs into small, distributed-memory blocks to create small scratchpad memories.

The XP2 family has as many as 12 preimplemented DSPs with pipelined MAC (multiply/accumulate) functions and as many as four PLLs (phase-locked loops) that allow designers to align and synthesize clocks in their designs. The family includes I/O capacities ranging from 86 to 540 pins and features flexible I/O-buffer support for popular I/O standards, such as LVCMOS (low-voltage CMOS), SSTL (stub-series-terminated logic), HSTL (high-speed-transistor logic), and LVDS (low-voltage-differential signaling). The buffers also support DDR2 memory interfaces at 400 Mbps, high-performance ADCs and DACs at speeds as high as 750 Mbps, and 7-to-1 LVDS-display interfaces at speeds higher than 600 Mbps. LatticeXP2 comes in CSBGA, FTBGA, FPBGA, TQFP, and PQFP packages.

With the new device, the company has also improved its ispLever FPGA-programming software. It improves device performance by as much as 46%, with an average increase of 12%. The company has also reduced run-time by as much as 70% and an average of 30%. The new version, ispLever 7.0, also includes a new power calcu-lator and the new Reveal logic analyzer. For $1495 extra, Lattice also offers the ispLever Pro IP (intellectual-property) bundle, which includes cores for DDR, DDR2, FIRs (finite-impulse-response) filters, FFTs, and triple-speed MACs.

Lattice is now offering samples of the first member of the LatticeXP2 family, the 17,000-LUT LatticeXP2-17, in 208-pin PQFPs, 256-ball FTBGA, and 484-ball FPBGA packages. The company plans to bring the entire device family to market this year. Lattice expects the LatticeXP2-17 to sell for $12 (100,000) for delivery in 2008, and ispLever will become available this July.