News and New Products

Sierra releases IC place-and-route tools for 45-nm era

By Michael Santarini, Senior Editor -- EDN, 5/28/2007

Sierra Design Automation has released a new version of its Olympus physical-design suite for 45-nm-IC design with three new tools for layering and buffer swapping, multicorner-clock-tree synthesis, and shape-based DRC (design-rules-checking)-accurate routing. As the 65-nm node becomes more mainstream and as the use of the 45-nm node increases, older tools for the 130-nm process node, including those for placement and routing, design-timing, and closure, increasingly can’t handle the size and complexity of newer process geometries. “Most of the place-and-route tools on the market today were built for the problems of 130-nm design, when the big problem was timing closure,” says Sierra’s chief executive officer, Pravin Madhani.

However, at finer process geometries, manufacturing closure is the problem, and addressing it requires a DFM (design-for-manufacturing)-driven place-and-route system, according to Sudhakar Jilla, director of marketing at Sierra. The company built the Olympus suite for the new batch of challenges that arise in the 65- and 45-nm-design era. In 2003’s DAC (Design Automation Conference), the company introduced a much speedier router than competing tools. At 2004’s DAC, the company introduced multimode design and analysis for power savings; 2005’s DAC brought Sierra’s lithography-driven routing engine for 65-nm design and close coupling with Mentor’s Calibre physical-verification lineup. This year at DAC, which takes place June 4 through 8 in San Diego, Sierra will introduce Olympus SOC (system on chip) for the challenges of 45-nm design.

Jilla says that the problems now emerging for 45-nm design are resistance spikes and variability. “The resistance-per-unit length has doubled from 65 to 45 nm, while capacitance has stayed fairly stable,” says Jilla. “As a result, the RC-unit length has significantly jumped from 90 to 65 to 45 nm. On top of that, there is now a large variation in resistance across a die. … If a circuit has a given performance or clock skew, you now have to guarantee that the circuit works over all the process corners. One of the big variables is resistance, which makes the clock tree and the performance fluctuate. Thus, for 45 nm, you need technologies to compensate for these problems.” At the 45-nm node, resistance in vias is two to three times greater than resistance in vias at the 65-nm node. This increase means that designers must try to limit the number of vias they use.

Traditionally, layout groups have dealt with increased resistance and capacitance by adding buffering—breaking down long wires into a series of smaller wires. But that technique doesn’t work so well at smaller process nodes. “Now that you have resistance becoming such a big factor in determining a design’s performance, it is no longer sufficient to simply break up a wire into little pieces,” says Jilla. “You now have to think about what layer that wire is going onto.” Higher layers in the layer stack tend to have lower resistance than middle layers, but you can’t put an entire design into just the upper layers. To address the resistance-related issues, Sierra has introduced the FalconGR engine, which dynamically makes trade-offs between layer assignments and buffering to determine the best area-versus-delay decisions.

To deal with, resistance variability, Sierra has developed a multicorner-CTS (clock-tree-synthesis) tool that works with other tools in the flow. “Resistance fluctuates so widely across a die that you really can’t pin down your performance unless you measure all the corner cases, [accounting for] resistance fluctuation,” says Jilla. “Every tool in the place-and-route flow has to take multicorner CTS into account. You need multicorner placement, CTS, and routing to ensure that you’re not going to have problems with performance.”

Design groups traditionally derive realistic performance targets for their clock trees using one corner and then try to make the rest of the design meet that performance number by balancing the amount of delay between the wires. This approach minimizes clock skew. However, the one-corner method doesn’t work at the 45-nm process node. “If you build a clock tree in one design corner, and now you check the clock skew at different design corners, you will see a huge fluctuation in skew going from 60 psec for the corner that you built all the way to 140 psec at a different corner,” says Jilla.

To address this problem, Sierra’s multicorner-CTS tool takes into account intercorner and intracorner skew. A sample design with a conventional one-corner CTS shows a 145-psec skew, but, with the multicorner CTS engine, a design with nine corners has only 87-psec skew—a 40% decrease. The tool also reduces the hold-buffer area by 54% and total area by 18%. Further, if you build a clock tree with more corners, each new corner you add further decreases the amount of fluctuation. If you add enough corners, the skew becomes minimal to nonexistent.

Sierra has also tuned up its routing engine to better handle the large rule decks for the 45-nm process and has added support for model-based DRC. With the advent of finer process geometries, the number of DRC rules increases. In addition, today’s routers now must account for extensive lists of DFM rules. Jilla notes that routing is traditionally a four-step process: global routing, assigning tracks, detailed routing, and postprocessing; prostprocessing has become the longest step in the 65- and 45-nm-design era and often requires users to run several iterations between DRC and the physical-implementation flow to ensure that their designs comply. To minimize iteration and shorten the postprocessing step, Sierra has added correct-by-construction features to the global-routing and assigning-tracks steps of the router. The company has also added a shape-based DRC engine to all its router engines to ensure that the tool creates DRC-compliant layouts. The multithreaded shape-based router has an average run speed of 260,000 polygons/sec and routes 5 million nets—123.5 million polygons—in a 90-nm, metal-layer process with a DRC check that takes only 25 minutes. It routes 20,000 nets, or 5.59 million polygons, in a 65-nm, metal-layer process with a DRC check that takes 2 minutes. The company provides no runtime numbers for 45-nm process. The base configuration of Olympus SOC sells for $1.6 million per seat.