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Microprocessor Forum recap: Balancing power and performance

By Robert Cravotta, Technical Editor -- EDN, 5/30/2007

Balancing processing performance with energy efficiency continued to be the theme at this year's Microprocessor Forum. The forum is an opportunity for companies to present not just new processors but to provide a first technical look at upcoming processor architectures—so some of the information presented can apply to devices that are not yet available.

Intel started off the forum with several presentations that provided a benefits summary of the upcoming devices using the company's 45-nm process; a technical overview of the 45-nm Intel Core Microarchitecture (Penryn); and explorations of the technical implications of emerging demands for Tera-scale computing, including more scalable memory architectures, improving management of caches, and QOS (quality of service) memory-resource distribution.

A Mears Technologies presentation described the MST (Mears Silicon Technology), which uses a channel-replacement technology to derive an enhancement in drive current along with a 60% reduction in gate leakage, compared with an 85-nm PNO (plasma nitrided gate) CMOS baseline.

AMD introduced the "Griffon" architecture and the "Puma" platform targeting mobile computing. Both include a new integrated memory controller featuring a DRAM pre-fetcher, fixed analog and I/O voltage planes, and separate voltage planes with independent frequency and voltage scaling for each CPU core. The architecture also features an on-die NorthBridge, HyperTransport 3 I/O links with support for dynamic link width scaling, autonomous hardware power management, and multipoint thermal control, which uses multiple on-die thermal sensors to automatically reduce the system's power state when the temperature exceeds defined limits.

Another session focused on automotive systems. A presentation by Denso focused on the future requirements for microprocessors, such as Denso's 32-bit NDR processor core, in automotive embedded systems including body electronics and navigation. Freescale introduced the MPC5121e, which features a Power Architecture-based processor core integrated with a multimedia acceleration core, a 2D/3D graphics acceleration core, a 3-plane blend display interface unit, and a multiclient DRAM controller. Parimics presented its hardware and software approach for image analysis, which relies on layers of arrays of processing elements (76,800 per die).

Renesas presented information on the SH-Navi2V, which integrates a 600-MHz SH4A processor core with a 2D graphics accelerator and an image-recognition engine; the image-recognition engine supports 200 APIs to ease programming for template matching. Outside the forum, Renesas announced that its controller roadmap includes a new microcontroller architecture based on the M16C and H8 architectures. Technical details on the architecture will not be available for approximately a year.

NTT DoCoMo Communications Laboratories presented information about the cell-phone technology requirements for Super 3G LTE (Long Term Evolution) and research for 4G wireless systems. IPFlex presented its dual-core, dynamically reconfigurable processor based on the "DAPDNA-IMX" architecture. The presentation included details on the 955 PE (processing element) matrix and the software-development flow to target this type of architecture.

Nvidia discussed the SM multithreaded multiprocessor with 8 SP thread processors, which can handle 768 threads in hardware. The company also touched on the CUDA (Compute Unified Device Architecture) programming model. Stream Processors presented details about its Storm-1 SP16HP architecture, which aligns with streaming applications that are compute-intensive on parallel data with limited locality of reference. Stretch presented its S6 architecture, which adds video surveillance to the list of target applications with its second-generation ISEF (instruction set extension fabric) optimizations.

AMCC presented its dual-core Titan, a Power Architecture-based processor implemented with Intrinsity's four-phase clock Fast14 technology, which can deliver 2-GHz operation on each core with a power consumption of 2.5W per core (at 1.0 V on TMSC 90-nm GT technology node).

ARM presented its first processor core, the Cortex-M1, targeted to reside in an FPGA device; the core will be available for Actel FPGA devices this July. ARM also presented information about multicore support for the ARMv7 architecture, which touched on cache coherence, a coherence accelerator port, an 8-bit extension to the ARMv6 exclusives for SMP support, and support for multiple paravirtualized operating systems. MIPS introduced its 74K core, which builds on the MIPS32 24KE core.

Qualcomm presented information about its Scorpion processor, an instantiation of the ARMv7 microarchitecture in a 65-nm LP technology combined with a VeNum ("Vector Numerics") multimedia engine, and the Snapdragon mobile platform. Tensilica presented its software-programmable Diamond 388VDO dual-core video decoder/encoder that uses a stream and a pixel processor to improve the performance of CABAC (context-adaptive binary arithmetic coding) compression. Ceva was at the show but did not formally present the details of the 32-bit CEVA-Teaklite-III core targeting home-entertainment audio, which is backward compatible with previous versions of the core. The core includes FFT acceleration, Huffman acceleration, and dedicated audio instructions.