Columnists

DAC stumbles looking to find firm future

Another lackluster conference highlights the challenges EDA companies face.

By Maury Wright, Editorial Director -- EDN, 6/21/2007

The June 2007 rendition of DAC (Design Automation Conference) in San Diego again reveals an uncertain direction for the chip-design community.

Moreover, organizers appear to be looking for some way to stop the trend of a shrinking exhibition and attendee list. This year, the organizers in part tried to promote an automotive theme, although the effort has come off flat at best. For sure, the conference continues to offer valuable education to chip designers. But it's the chip designers—especially in leading-edge processes—that are shrinking in number and certainly working for different types of companies from those they worked for just a few years ago.

EDN and TSMC hosted the EDAC (EDA Consortium) executive reception and panel on Sunday to kick off the show. That panel, which EDN Executive Editor Ron Wilson and Electronic News/Electronic Business Editor in Chief Ed Sperling co-moderated, pitted a group of senior IC-design managers against a group of marketing executives from the fab and EDA market. Wilson summarized some of the key points from the panel in his blog (see "Is IP reuse, rather that an ESL, the next level of abstraction for SoC design?"). I'd like to add a few of my own thoughts on that panel and relate them to what I see as another lackluster DAC.

First and foremost, I think you can draw some conclusions from the chip-designer side of the panel. Major fabless-IC vendors Broadcom and Qualcomm were represented, but companies such as Cisco, Apple, and Nokia were not. ASIC-design house eSilicon was represented. But there were none of the ASIC designers working for end-product companies that would have been front and center on such a panel just a few years ago.

Now, I've been quick to claim in the past that the shrinking number of ASIC starts was not as bad as advertised. I still think the analysts that track those statistics fail to account for the ASSPs that are increasingly designed by the likes of Qualcomm. I'm sure that Cisco is still doing a fair amount of ASICs. But in what technology is Cisco working, and how does that align with the presumed hot issues at DAC?

The major issue at DAC this year continues to be how to verify SOCs (systems on chips) built in the latest process technologies. The panel clearly indicated that Broadcom and Qualcomm care about that. But who else cares? The list is short. Intel cares but uses internal tools. Memory vendors need the latest process technology, but they don't need to fully verify memory blocks thanks to ECC and other technologies that correct errors.

Ironically, I'm not sure that the EDA vendors themselves really care. Mentor Graphics has certainly done well with verification tools. But reading between the lines at the Sunday panel, tool vendors may not believe that there's sufficient interest—read "customers"—to go and innovate the system-level approach that's really needed in state-of-the-art chip design. Now, TSMC and other fabs clearly need the fabless chip vendors to fill their factories, and, certainly TSMC, among other fabs, has deepened its level of support for leading-edge chip designs.

Meanwhile, I suspect that the likes of Cisco are churning right along at less ambitious process nodes. The big communication-equipment vendors can't fit everything into one chip anyway, and they are relying on off-the-shelf ASSPs in some cases. Apple likely has no interest in designing an SOC for, say, the iPod. It wants to churn the technology twice a year anyway to capture the upgrade market as well as new customers. Apple will never sell enough of a single model to justify a custom SOC.

In short, this DAC has been more of the same. As I wrote last year in "DAC disappoints: Maturing segment needs a jumpstart," there have been no real significant innovations in EDA. The verification story is getting stale. In his blog, Wilson suggests that preverified IP (intellectual property) could perhaps solve the problem. Alas: The news isn't necessarily good there, either. At the end of a Monday panel entitled "Just who is providing the IP?" longtime EDA industry follower and moderator Peggy Aycinena pessimistically noted that the panel on IP was almost exactly like one held five years ago. And that observation clearly calls into question the industry's progress on IP reuse.