IP expert advice: How to make the IP ecosystem work for you

If integrators want to minimize their risk in using a particular IP core and shorten their product development cycle, they need to understand the IP ecosystem.

By Kathy Werner, VSI Alliance -- Electronic Business, 6/20/2007

One of the concepts IP integrators have to embrace is that IP does not exist in a vacuum. By understanding the influence of IP throughout the design chain and through some manufacturing operations, processing, and test, integrators can minimize their risk in using a particular IP core and shorten their product development cycle. However, this requires an understanding of the IP ecosystem.

Taken from its original biological background, the term ecosystem applied to semiconductor IP means how the individual IP cores interact with all of the other parts of and operations involved with a SOC. Looking at a diagram representing the IP ecosystem, we see that vendors as well as integrators should be concerned about the effect a particular piece of IP has on several SOC development activities.

The interaction between IP and design activity occurs at many points, some obvious and some not so obvious. For example, qualifying IP prior to its use in an SOC benefits both vendor and integrator. A good quality mechanism lets IP vendors gauge the goodness of their products and how well they will fit anticipated integrator requirements; provides a common communication platform between vendor, user, and foundry; and then gives the integrator a way to compare IP from different vendors to choose the best one for a particular design.

It is important to note the influence semiconductor foundries have on IP qualification, indicated by the tan arrow in the diagram. Foundry input helps IP vendors develop products that are qualified by one or more foundries. This aids in the evaluation of a family of IP—in other words, the same functional IP core ported to different processes—and reduces the risk of using that IP. Foundry qualification also enhances the models an integrator needs for verifying that a particular piece of IP will work as planned in a specific application. Finally, foundry input on IP development also aids foundries during chip manufacturing, because they have already processed test chips containing that IP to qualify it, enhancing the yield of chips using that IP.

Using a standard approach to IP assessment and evaluation, covering a variety of IP types—such as hard, soft, and verification—puts a common framework around the assessment and evaluation mechanisms. This is very important for providing a level playing field for making the interfaces between the various SOC development steps as smooth as possible. Protecting IP value is also critical throughout the design chain, including operations such as IP tagging and encryption, as is IP transfer from vendor to integrator and on to chip manufacturer.

The IP ecosystem, as shown in this figure, can be laid on top of the SOC design chain. Chip design requires the cooperation of several types of organizations—design groups, foundries, EDA tool providers, test developers, and others—all connected with a group of standardized descriptions and interfaces. This represents an SOC design ecosystem. The IP ecosystem works in much the same way. Common approaches to evaluation and other IP–related tasks simplifies the job of IP providers; sets expectations for integrators and helps them realize those expectations; and simplifies the integrator's interfaces with EDA vendors, foundries, and other supply -chain providers.

This is the job of an IP standards organization such as the VSI Alliance: to look at each stage of the IP ecosystem and develop standardized solutions enabling companies to minimize risk and maximize profit when integrating IP onto their SOCs.

Kathy Werner is president of the VSI Alliance.