News and New Products

SOC design and CPU design begin to converge

By Ron Wilson, Executive Editor -- EDN, 6/7/2007

Ever since the emergence of RTL and cell-based synthesis, the teams that design high-end microprocessors have worked differently than the teams that design SOCs. That's been an industry axiom. But it may be an axiom on its way into history.

Large teams—hundreds of people—design the big CPUs. They implement critical circuits such as data paths, registers, and some control structures either with custom cells or with hand-crafted structures to wring the best possible operating point out of the process. Often, that process is being developed in parallel with the CPU circuitry, and in response to its needs. The designers use RTL synthesis is used only for the noncritical portions of the chip.

Things have been entirely different in the SOC world. Engineers have assembled SOCs from a variety of reused IP and synthesized RTL blocks. They generate memories using off-the-shelf compilers, again from third-parties. If any custom work became necessary, it was generally of an analog or mixed-signal nature, and would be performed by outside design houses and carefully encapsulated within a cell that the standard place-and-route tools and analysis tools could understand.

But this is changing, at least according to some panelists at a DAC luncheon event this week. At the ARM- and Magma-sponsored panel on Super-SOC Design, several panelists suggested that the two apparently disparate design styles are beginning to converge.

"Probably, yes, the two styles are converging," said Srinivas Nori, senior engineering manager for graphics processors at Microsoft. "There is a trend for SOCs to combine cores on one die, just as the microprocessor people are doing."

Edward Wan, senior director of Design Technology Support at TSMC, agreed. "We see customers doing integration of both high-speed blocks and low-power blocks in one design. This is requiring the designers to use microprocessor-style techniques on some parts of the chip. Today you can have a cell-phone chip with an applications processor that can run at a gigahertz and a baseband processor that can standby at a microamp—sitting right next to each other. It demands a process that provides multiple threshold voltages, and it demands that the design team use multiple design methodologies on the same die."

Nori agreed. "We are already using mixed methodologies on the chip. It's a balancing act."

At the same time, ARM fellow Rob Aitken observed, microprocessor design styles are moving toward more SOC-like results. "You can't just make the same old core go faster any more," he said. "Especially in their way of dealing with power—spreading the work across multiple cores—the methodologies are convergent."

Certainly there are still important differences. Magma vice president of strategic technology Roger Carpenter pointed out that the maximum frequencies used in CPUs have always been greater than those on SOCs, and the gap has widened lately.

It should also be said that structurally, CPU design teams tend to be geographically dispersed but contained within one company. SOC designs still tend to turn to externally developed IP for the critical blocks that require custom circuits or hand placement. And yet the similarity is striking. One can envision a time when a high-end CPU, comprising multiple CPU cores, graphics cores, memory structures, and bus logic, will look very much like an SOC with multiple CPU cores, specialized DSP cores, memories, and interface logic. The methodologies may also be remarkably similar. The difference may turn out to be in the terminology.