Toshiba touts 3D NAND cell array as ticket to higher density NAND

By Colleen Taylor, Contributing Editor -- Electronic News, 6/12/2007

In a development that the company claims could meet a future demand for higher density NAND flash memory, at the VLSI Symposium in Japan today Toshiba Corp. announced a new three-dimensional memory cell array structure that the company said enhances cell density and data capacity without relying on advances in process technology and with minimal increase in the chip die size.

In the new structure (see image below), Toshiba said, pillars of stacked memory elements pass vertically through multi-stacked layers of electrode material and utilize shared peripheral circuits. Typically, advances in memory density reflect advances in process technology, but Toshiba claimed that its new approach is based on innovations in the stacking process.
 
Toshiba's etching technology drives a through-hole down through a stacked substrate, essentially a multi-layer sandwich of gate electrodes and insulator films. Pillars of silicon lightly doped with impurities are deposited to fill in the holes. The gate electrode wraps around the silicon pillar at even intervals, and a pre-formed nitride film for data-retention, set in each joint, functions as a NAND cell.  
 
According to Toshiba, its new array increases density without increasing chip dimension, as the number of connected elements increases in direct proportion to stack height. For example, a 32-layer stack realizes 10 times the integration of a standard chip formed with the same generation of technology.

The technology, however, is still in its beginning stages. Toshiba, which has laid claim to inventing NAND flash in 1986, said it will further develop this elemental technology to the level where it matches current structures in terms of security and reliability.



Source: Toshiba