Intel delves deeper into tera-scale

By Ann Steffora Mutschler, Senior Editor -- Electronic News, 6/13/2007

On the heels of last week’s Design Automation Conference, semiconductor industry powerhouses have not slowed down – in fact, there are four significant technical conference this week to keep everyone more than a bit busy, and the industry’s chip leader is active on all counts.

Intel Corp. is presenting papers this week on seven separate research advances at four conference that are meant to move the company closer to realizing its vision of tera-scale computing, namely, to allow future chip platforms based on tens to hundreds of cores.

At the 2007 Symposium on VLSI Technology, being held this week in Kyoto, Japan, Intel is detailing fast, scalable I/O with record energy efficiency in its paper, “Scalable 5-15Gbps, 14-75mW Low Power I/O Transceiver in 65nm CMOS.”

Randy Mooney, Intel Fellow and director of I/O research and Jerry Bautista, co-director of Intel’s tera-scale computing research explained to Electronic News that the goals of this project were to push I/O capabilities over industry-standard “FR4” boards, achieve industry-leading power efficiencies for greater than 10-Gbps I/O and allow dynamic power management with scalable circuits.

Test chips revealed that a new architecture systematically optimizes supply voltage, bias current and driver power efficiency, which is scalable from 5- to 15-Gbps per I/O channel. 

An inductive termination feature allows for passive equalization with no power cost, the two noted.  As a result, Intel researchers achieved scalable low power I/O from 14-mW at 5-Gbps to 75-mW at 15-Gbps.

Also at the VLSI Symposium, Intel is detailing the router in its 80-core research processor, first discussed in February.

Intel’s paper, “A 5.1GHz 0.34mm2 Router for Network-on-Chip Applications,” gives further technical details of the core-to-core router in the 80-core teraflops research processor, which it believes is one of the fastest and most compact routers in the industry today.

Features of fully non-blocking router include 5GHz+ clock speeds, a mesochronous link that allows for modular clocking, power management circuits, more than 100 gigabytes per second bandwidth per node and more than 2.6 terabits of on-chip bisection bandwidth.

Other Intel folks made their way to San Diego for the International Symposium on Computer Architecture(ISCA), the Programming Language Design and Implementation Conference (PLDI) and the International Conference on Measurement and Modeling of Computer Systems (SIG) where another five papers were presented by Intel researchers.

Links to papers will be added when available on conference sites.