Intel plans Itanium 'leapfrog' to 32-nm

By Colleen Taylor, Contributing Editor -- Electronic News, 6/14/2007

SAN FRANCISCO — At a briefing here this afternoon that was short on details but long on the company's big-picture progress, Intel Corp. revealed the roadmap for its high-performance Itanium processor family over the coming years.

On track for a late 2008 release is the company's next Itanium, codenamed "Tukwilla," a quad-core, single-die processor manufactured at the 65-nm processing node.

According to Diane Bryant, VP of Intel's digital enterprise segment, Tukwilla will boast twice the performance of Intel's dual-core Itanium 2 processor, and each chip will be capable of supporting eight threads.* 

In addition, Tukwilla will have a new platform architecture: the memory controller will be integrated in the chip, moving off of the front side bus interconnect. 

Also, a new mainframe-level RAS memory correction technology, "double device data correction" (DDDC), is meant to allow Tukwilla chips to continue running even in the event of two sequential DRAM device errors.

Intel's current generation Itanium offers a top clock speed of 1.6 Ghz; IBM's competing dual-core POWER6 chip, meanwhile, tops out at 4.6 Ghz. Bryant would not disclose details of Tukwilla's clock speed, but noted that unlike IBM, Intel has opted to focus on "performance through multicore parallelism, rather than through frequency."

Next in line after 65-nm Tukwilla will be a 32-nm Itanium offering codenamed "Poulson" — leapfrogging the company past the 45-nm node. 

"We want the process technology to mature before we come out with a larger die size processor [like Itanium]," Bryant explained. "But right now, we're further out in the [process technology] timeline than we want to be, so we're going to leapfrog 45-nm and go straight to 32-nm.

"The technology curve of reaching process maturity has improved for the mass of Intel. That reduction in time for reaching maturity on the process technology allows us to now just completely leapfrog a generation to go to 32-nm and still be very close to the leading edge." **
 
Beyond that, Bryant disclosed precious few details on Poulson, other than to say it would not ship until 2010, at earliest, and would feature a "massive on-die cache" for memory and boast more than four cores. After Poulson, Bryant said, would be an even more vaguely defined offering codenamed "Kittson."

Editor's notes: *This paragraph originally stated each core will be capable of supporting eight threads and was corrected to state each chip will be capable of supporting eight threads at 12:30pm eastern.
**These quotes were added to this story after its original publication at 12:30pm eastern.