Survey reiterates industry doubt of 450-mm wafers

By Colleen Taylor, Contributing Editor -- Electronic News, 6/20/2007

Although the semiconductor industry is indeed steadily moving toward higher yields and smaller process technologies, researchers say that a number of currently buzzed-about advancements are still a long way off from becoming a reality.  

According to a report issued this week from consulting services company Wright Williams and Kelly Inc. (WWK) based on a recent survey the firm conducted in conjunction with market research firm Strategic Marketing Associaties on equipment and process timing in the semiconductor industry, a majority of respondents within the industry said they do not expect to see EUV lithography, imprint lithography, or 450-mm wafers in production until 2013 or later.

In fact, the firms said, a whopping 39 percent of respondents indicated that 450-mm wafers would never happen in production manufacturing.

The report will not come as news to equipment industry heavy hitters at Applied Materials or Novellus; CEOs from each company told Electronic News last year that they are not expecting to see 450-mm wafers in production for at least the next ten years. Execs at Cadence Design Systems and e-Silicon have since echoed similar doubts about the reality of 450-mm feasibility.

The firm was quick to note that there is a bright side to this bit of stagnation in technology advancement. "We expect that fabs can plan on at least 5 years, and probably more, life from their current investments in 300-mm manufacturing equipment," Darren Dance, WWK's VP of technology, said in a statement.

The survey's outlook for industry advancement was not completely negative. More than half of survey respondents said that they do expect to see adaptive test, high k gate dielectrics, metal gates, and equipment with energy saving sleep states to come into production by 2010. And between 2010 and 2012, more than half of the survey's respondents said they expect to see 193 high immersion lithography, wafer-level reliability testing, and damascene gate formation.