Cadence buys litho pattern synthesis provider Invarium

By Ann Steffora Mutschler, Senior Editor -- Electronic News, 7/12/2007

To address the technical challenges of manufacturing at 45-nm and smaller process geometries, including new patterning challenges such as double patterning, printability and scaling of very fine features, semiconductor design tool market leader Cadence Design Systems Inc. reported today that it acquired San Jose-based advanced lithography-modeling and pattern-synthesis technology developer Invarium Inc. on Tuesday for an undisclosed sum.

Invarium says its pattern synthesis capabilities allow “superior” pattern resolution and faster yield ramp for designs targeted to 45-nm and smaller processes.

Cadence expects this acquisition to give customers a solution for functional and parametric yield improvement that detects, corrects, prevents and optimizes manufacturing effects on advanced geometry designs thanks to Invarium’s specific area of expertise, which is the development of pattern-synthesis technologies that allow photomask design and process optimization. The company’s tools span the entire manufacturing-process flow from mask making to lithography and etch, with industry-leading speed.

Roy Prasad, president and CEO of Invarium noted that Invarium’s layout-to-mask solution is being used by manufacturers of custom and memory designs at advanced process nodes, where the highest level of accuracy and widest process latitudes are required.

“At 45-nm and below, the semiconductor industry is looking at a new set of patterning challenges that include double patterning, printability and scaling of very fine features, and the margin for error is extremely small,” added Jim Miller, executive VP for Cadence’s products and technologies organization, in a statement. “The acquisition of Invarium will enhance Cadence's ability to address these challenges head-on.”

In other Cadence news, earlier this week, it detailed its work with the Japanese research consortium Semiconductor Technology Academic Research Center (STARC) in addressing 65-nm DFM challenges.

The companies have developed an advanced design flow meant to improve manufacturability and yield for 65-nm designs, which is based on Cadence’s Encounter digital IC design platform to provide STARC member companies with integrated and enhanced DFM and design for yield capabilities.

The two said they have been collaborating for more than 15 months to develop the flow.