Post a CommentOpinion: Signoff for manufacturability - an absolute necessity at 45-nm
Designing at the 45-nm node combines huge risks with the potential for huge rewards. Companies who fail to complete their designs on time and miss their market windows may well go out of business. By comparison, companies who have the necessary expertise combined with appropriate "Signoff for Manufacturability" environment stand to reap huge rewards.
By Rahul Deokar, Cadence Design Systems Inc. -- Electronic News, 8/17/2007
The electronic design industry continues to push the limits of Moore's Law through smaller and smaller process nodes. As we reach 45-nm, manufacturing and process control becomes increasingly difficult, making it imperative that manufacturability issues be addressed much earlier in the design cycle to avoid costly re-spins and chip failures. In fact, a paradigm shift is evident in the all-important signoff analysis step of the digital design cycle.
Slight variations of temperature, duration, and chemical concentration in the manufacturing process result in physical changes in devices and interconnect. This leads to deviations in their electrical behavior, and now the designs that passed traditional sign-off standards might still fail in 45-nm silicon. The next-generation signoff solution needs to address these electrical, physical and manufacturing challenges, enabling designers to prevent silicon failures and better manage variations in timing, power, and signal integrity - both across a wafer and across the surface of a single chip.
Bringing six-sigma quality to chip design
Traditional static timing analysis (STA) fails to account for the variability inherent in semiconductor processes, making exaggerated pessimism a necessary evil. It introduces aggressive guard-band and multiple corners or scenarios, but as the number of scenarios increases, the number of analysis runs can increase greatly, making design convergence exceedingly difficult while straining resources, increasing costs, and stretching schedules. In addition, this multiple-corner approach is overly pessimistic and can report timing scenarios that have an extremely small likelihood of occurring. And this is precisely why statistical STA (SSTA) is emerging as the signoff solution to carry the industry into the future.
SSTA makes it possible to break the barriers of corner-based analysis and to holistically model the factors affecting process variation in a single analysis run. It obviates the need for multiple corners and removes much of the inherent pessimism. This allows for reduced guard-banding, which results in decreased area and power consumption while improving chip performance. SSTA also enables designers to explore potential trade-offs and to evaluate parametric yield for a desired performance target.
The underlying SSTA modeling must include systematic variations due to chemical-mechanical planarization (CMP), lithography, mechanical stress, and etching effects. It should account for the way in which light will pass through the photo-masks and lenses, how it will react with the chemicals on the chip surface, and what the resulting structures will look like and how they will perform in silicon. The signoff solution then should calculate the impact of these systematic effects on timing, power, reliability, and so forth. In addition, devices experience random defects and variations, which can cause device mismatch. Spatial or mesh-based techniques should be used to model the variation of interconnect and device parameters for different regions of the die.
In addition, at 45-nm increased power density and advanced low power techniques have lead to wider on-chip temperature variations. Different areas of a chip may vary by 40 degrees C or more, depending on switching activity. Furthermore, the barrier layer on top of the die acts as a "thermal blanket," resulting in a thermal differential of as much as 45 degrees C between the top-most metal layer and the inner silicon surface. The 45-nm signoff solution should accurately model temperature gradients in the context of silicon, package, and board, and account for their impact on power, voltage (IR) drop, electromigration, and timing.
Moving to 45-nm technology offers many advantages with regard to creating state-of-the-art silicon chips. Unfortunately, the associated complexity and variability strain conventional signoff analysis solutions. In order to take full advantage of the 45nm gains, the electronic design industry must be prepared for a paradigm shift towards a signoff analysis that will enable "signoff for manufacturability."
The new signoff solution will account for systematic and random variations, CMP, etch, lithography, and thermal and electromigration impact to evaluate timing, power, and reliability. At 45-nm, it is imperative to use a single signoff engine for both implementation and final verification, allowing design engineers to perform "signoff in the loop" - significantly improving predictability, productivity, and performance. It will usher in the much-anticipated "electrical DFM" that provides multi-objective placement, physical synthesis, and routing optimization while comprehending the full spectrum of physical and electrical implications of manufacturing.
Designing at the 45-nm node combines huge risks with the potential for huge rewards. Companies who fail to complete their designs on time and miss their market windows may well go out of business. By comparison, companies who have the necessary expertise combined with appropriate "signoff for manufacturability" environment stand to reap huge rewards.
Rahul Deokar is the product marketing director for Encounter digital IC design at Cadence Design Systems Inc. with focus on digital timing, and signal integrity including variability and manufacturability effects. Prior to Cadence, Deokar worked in R&D on timing analysis and logic/physical synthesis at Ambit Design Systems. Before Ambit, he was in the advanced R&D team at Bell Laboratories, Lucent Technologies. Deokar received an M.S. in Computer Engineering from Iowa State University and an M.B.A from Santa Clara University.
