64-core processor tip of the multicore iceberg for startup Tilera

By Colleen Taylor, Contributing Editor -- Electronic News, 8/20/2007

Promising major advances to multi-core architecture, startup Tilera Corp. today launched the TILE64, a processor containing 64 full-featured programmable cores.

The Santa Clara, Calif.-based fabless semiconductor maker claimed each core is capable of running Linux and purportedly delivers 10 times the performance and 30 times the performance-per-watt of the Intel dual-core Xeon, and 40 times the performance of the leading Texas Instruments DSP.

TILE64 is the first in a family of Tile Processor chips based on an architecture that the company claims can scale to hundreds, and even thousands, of cores. The processor's initial target markets include the embedded networking and digital multimedia markets, Tilera said.

Tilera's executives have not minced words on the importance they place on the company's multicore technology. "This is the first significant new development in chip architecture in a decade," Tilera's President and CEO Devesh Garg said in a statement. "We developed this new architecture because existing multicore technologies simply cannot scale beyond a handful of cores. Moreover, customers have repeatedly indicated that the current multicore software tools are very primitive because they are based on single-processor-core models. We're introducing a revolutionary hardware and software platform that has solved the fundamental challenges associated with multicore scalability."

Tilera was founded in 2004 as a spin off from research done at MIT by Tilera's co-founder and CTO Anant Agarwal, who first created the mesh-based multicore architecture in 1996. This project received multi-million dollar DARPA and National Science Foundation grants and spawned the development of the first tiled multicore processor prototype and associated multicore software in 2002, the company said.

Tilera said its new architecture eliminates the on-chip bus interconnect, which is a kind of centralized intersection that information must flow through between cores within the chip, or before it leaves the chip. The company claims that as engineers have added more cores to chips, the bus has created an "information traffic jam" because packets from these cores all must travel to one central point. Instead, Tilera's iMesh technology places a communications switch on each processor core and arranges them in a grid fashion on the chip, which effectively creates a two-dimensional traffic system for packets. Because the aggregate bandwidth is orders of magnitude greater than a bus, and the distance between cores is shorter, the iMesh technology can be leveraged to create grids as large or small as an application requires, Tilera claims.

In addition to iMesh, the TILE64 processor integrates four DDR2 memory controllers and a complete array of high speed I/O interfaces, including two 10 Gbps XAUI, two 10 Gbps PCIe, two 1 Gbps Ethernet RGMII, and a programmable flexible I/O interface to support interfaces such as compact flash and disk drives. Also, according to Tilex, the TILE64 delivers two streams of broadcast-quality, high-definition H.264-encode capability in a single chip, and more than ten streams of encode for high-definition video conferencing applications. (See TILE64 block diagram below for more.)

The TILE64 processor is available now in three different device variants based on frequency and I/O capabilities. Production pricing for the TILE64 family starts at $435 in 10K unit quantities. Tilera said its roadmap also includes plans for a 36-core and a 120-core device. Tilera said it has a dozen customers who are currently integrating the TILE64 processor into products in the advanced networking and digital multimedia space.


TILE64 block diagram


Source: Tilera, August 2007