In computers, communications, and consumer electronics, the transition from parallel to high-speed serial-data transmission is creating new design challenges. Increasing data rates push more bits per unit time through the same interconnect link, entering the multigigabit-per-second regime and creating substantially tighter timing budgets. Because of high-frequency interconnect losses, higher data rates also exacerbate ISI (intersymbol interference). Moreover, to achieve still faster data transmission, many standards allow several serial links to operate in parallel, creating multilane configurations, in which crosstalk plays yet another important role.

As a result, you must more closely manage the characterization of interconnect reflections, losses, and crosstalk. You must also differentially perform this characterization, and do it in the frequency, rather than the time domain, using so-called S-parameters (see sidebar “S-parameter backgrounder”). S-parameters provide quantitative insight into the causes of bit errors, BER (bit-error-rate) degradation, jitter, ground bounce, and EMI (electromagnetic interference). You can also measure crosstalk by using S-parameters to characterize signal transfer among adjacent transmission-line pairs. Many electrical standards, such as SATA (Serial Advanced Technology Attachment), PCIe (Peripheral Component Interconnect Express), Fibre Channel, and 10GbE (10-Gbps Ethernet), now use S-parameters in their compliance-test procedures. The umbrella term “SDNA” (serial-data-network analysis) describes differential serial-data-compliance testing and differential characterization of serial-data components.

The traditional S-parameter-measurement tools are VNAs (vector-network analyzers). These instruments are powerful, but that power may well be their undoing, because they achieve their accuracy with the aid of extensive calibration procedures. For SDNA applications, these differential calibration procedures can be excruciatingly lengthy and difficult to follow, resulting in long test times and sensitivity to human error. Electronic calibration modules for VNAs are available, but they operate only at frequencies that are relatively low for most SDNA applications. Moreover, the cost of VNAs tends to be higher than that of the instruments that most digital designers have on their workbenches.

TDR (time-domain-reflectometry)-based S-parameter measurement tools have proved to be cost-effective, easy to calibrate and use, and accurate enough for SDNA (see sidebar “TDR-based S-parameter measurements”). They also provide higher throughput than VNAs. For example, by using TDR and postprocessing software, you can obtain a differential insertion-loss measurement within a minute instead of the 15 minutes or so a VNA can require. Moreover, VNAs can’t measure directly to dc, and on long devices under test, such as cables, they can take a long time to accurately measure low frequencies. Most VNAs also compute systems’ differential response from single-ended measurements because, until recently, more accurate direct-differential measurement was too difficult and expensive.

TDR-based systems can directly measure dc and low frequencies. For example, by simultaneously firing multiple sources, Tektronix’s DSA8200 and IConnect S-parameter-measurement system can directly obtain true-differential TDR and S-parameters. IConnect also allows the acquisition of records as long as 1 million points, a requirement for S-parameter measurements on long devices, such as cables. Finally, the typical cost of a TDR-based system can be as little as half that of a VNA system that makes comparable SDNA measurements, and the TDR system provides higher time-domain resolution than does a VNA with comparable bandwidth. Several misunderstandings exist about TDR-based S-parameter measurements (see sidebar “Misconceptions about TDR-based S-parameter measurements”). Overall, TDR-based S-parameter-measurement systems provide an easy-to-use, high-throughput approach to performing S-parameter-compliance tests in accordance with many digital standards as well as tests used in characterizing digital devices that operate at gigabit-per-second speeds.

Start with the most basic requirement for TDR: providing sufficient resolution for locating faults in a device package or on a PCB (printed-circuit board). The IPC (Institute for Printed Circuits) document TM-650 2.5.5.7a defines TDR resolution as “the resolution limit … wherein two discontinuities or changes on the transmission line … begin to merge together … According to this definition, the resolution limit is half the … 10 to 90% rise time or 90 to 10% fall time (depending on whether the TDR response is calibrated with a short or open circuit)” (Reference 1).

Using Table 1, IPC TM-650 summarizes the resolution and TDR rise-time requirements for typical surface microstrips in air and on an FR4 PCB (Figure 1). (In FR4, propagation velocity of electromagnetic waves is approximately 2×10⁸m/sec—approximately two-thirds that in free space.) A board’s inner layer, or stripline, is more representative of a typical board run. In addition, it is useful to provide resolution data for propagation in air. For a stripline, assume a propagation of 0.446 times the propagation velocity of light in free space. Table 2 summarizes the resulting resolution data. Now look at a practical situation. On a typical TDR-demonstration board (Figure 2), the resolution structures are reasonably close to the board’s 2.4-mm S connector (see sidebar “Precision microwave-connector care and compatibility”).

Figure 3 presents the results of TDR testing with a 15-psec reflected-rise-time TDR module, with the signal launched from the left to access the 1.25-mm structure and the signal launched from the right to access the 2.5-mm structure. Clearly, on the structure with 2.5-mm separation, the two discontinuities have perfect resolution, whereas on the structure with 1.25-mm separation, you start to lose resolution. (The trace on the demo board is a microstrip, and, according to Table 1, there is a different limit on the resolution for microstrips.) The interesting question is, however: What happens for spacing shorter than 1.25 mm between discontinuities? The discontinuities do not disappear; they simply become one discontinuity. Clearly, then, when a failure analyst attempts to locate a single discontinuity, even a submillimeter discontinuity is observable with the TDR module. The following is an important conclusion: With 15-psec reflected rise time, an advanced module can achieve submillimeter resolution.

When using a TDR-based S-parameter measurement system for characterization or for a compliance test that a specific standard defines, it is important to know what the rise time must be to permit accurate measurements or testing. When specifying the rise time, standards focus primarily on the maximum, or slowest, rise time and look at the minimum rise time only as an informative parameter. SATA test procedures, for example, state the required minimum rise time, but then a footnote clarifies: “Failures at minimum rate have not been shown to affect interoperability and will not be included in determining pass/fail for interoperability testing” (Reference 2). So, for most standards, the question for a designer remains: What is the TDR rise time I need to test in accordance with the standard for compliance with a given specification, at a given data rate, with a given S-parameter bandwidth?

A recent study of standards revealed a clear trend in which rise times for first-generation standards, such as InfiniBand SDR (single data rate) and PCIe (Peripheral Component Interconnect Express), constituted a substantially smaller portion of the bit duration, or unit interval, than those of the second-generation standards, such as InfiniBand DDR (double data rate), PCIe 2.0, and 4-Gbps Fibre Channel, or third-generation standards, such as 8-Gbps Fibre Channel and 10GbE (gigabit Ethernet). You can draw an approximate dividing line between the generations of standards at 3.125 Gbps for the first- to second-generation transition and 6.5 Gbps for the second- to third-generation transition. The rise time constituted approximately 15% of the bit duration for the first-generation standards, 20% for the second generation, and 25% for the third generation. All rise times are 20 to 80% of the transition time (Table 3).

A designer who uses a TDR rise time that is 50% faster than the rise time of the devices in the controlling standard can achieve complete characterization of the channel with a more-than-adequate guardband. Note that TDR rise time is the time it takes a signal to traverse 10 to 90% of the transition range, which provides an additional guardband compared with the standards’ 20 to 80% rise-time specification. This assumption ensures that the rise time is sufficiently fast for characterization. If you need to slow down the rise time, you can either mathematically filter the oscilloscope or use sufficiently lossy cables or filters. Using this 50% guardband assumption specifies how much TDR rise time several standards require.

Typically, receiver dynamic range is the difference between maximum and minimum measurable power—P_MAX and P_MIN (Figure 4a). System dynamic range is the difference between the nominal power of the source (P_REF) and the minimum measurable power (P_MIN, Figure 4b). In TDR-based S-parameter measurements, P_MAX relates to a sampling module’s maximum operating specification and is less relevant when you focus on passive-component, or interconnect, measurements. As a consequence, system dynamic range matters for serial-data-interconnect characterization.

You may wonder how the definition of dynamic range relates to serial-data dynamic-range requirements. Dynamic range is, in essence, the difference between 0 dB and the noise floor. The accuracy of the measurement at a given frequency depends on the difference between a measurement level (P_MEASURED) and the noise floor (P_MIN). If your device under test has a measured noise floor of X dB below the measurement-reference level, you can show that the accuracy, or error, in percentage points relates to X dB below the reference value by the following equation:

Note that, in the frequency domain, because the signal and noise add vectorially, the equation shows worst-case error when the noise vector is in phase or 180° out of phase with the signal vector. Additionally, you can show that the total peak-to-peak ripple, the error-circle diameter in Figure 5, on that signal is Y dB using the following equation: Y dB=20[log(100%+accuracy%)–log(100%–accuracy%)].

This equation includes both the positive and the negative ripple on the waveform. You can now show accuracy that you can achieve depending on how far the dynamic range is below the measurement level (see Table “Accuracy versus dynamic range below measurement level”). For a typical characterization in any of the serial-data standards, you would want to measure a voltage no smaller than approximately 10% of the full-signal amplitude. Such a voltage glitch can result from reflections or from crosstalk from an adjacent differential-line pair. A voltage glitch of this type still provides an 80% eye opening (Figure 6).

It is adequate to measure this voltage glitch with 10% accuracy, which translates into accuracy that is 1% of the full-signal amplitude). The minimum measured voltage size and accuracy requirements for 10%±1% at 0.5, 1V, and 2V signals are 50±5, 100±10, and 200±20 mV, respectively. Using the curves of Figure 7, you can determine that a signal that is 10% of the total amplitude is –20 dB. To measure this signal with no more than 10% error, the noise floor must be another 20 dB below the measurement level, making the total dynamic-range requirement 40 dB.

Later generation standards place less stringent requirements on characterization of digital components. In the first- and second-generation standards, designers talked about characterization to the clock’s fifth harmonic, even though the standards required much less stringent compliance testing. In third-generation standards, designers talk about characterizing to the third harmonic. Overall, performing characterization to the fifth harmonic ensures adequate characterization bandwidth and provides designers with sufficient confidence. Using the fifth harmonic as a guideline, Table 4 provides the frequency requirements.

Figure 8 and Figure 9 present the dynamic range that TDR test equipment requires for SDNA applications. Notably, dynamic range degrades with frequency. The degradations result primarily from the steplike nature of the TDR-incident waveforms, which cause the incident power to roll off as 1/f. Table 4 shows how several standards relate to the dynamic-range and bandwidth requirements.

Based on expert user knowledge, this article identifies accuracy requirements for SDNA debugging, compliance, validation, and characterization and defines the requirements for SDNA applications. Those requirements are TDR rise time to resolve the smallest relevant discontinuity, TDR rise time for component characterization in accordance with various standards, and dynamic-range and bandwidth requirements for such characterization.