News and New Products

Startup Solido optimizes transistor-level statistical analysis

By Michael Santarini, Senior Editor -- EDN, 9/17/2007

Solido Design Automation (Saskatoon, Saskatchewan, Canada) wants to help analog and full-custom digital designers glean more insight from the statistical-analysis step of the traditional tool flow with its new SolidoStat tool set.

Statistical-timing analysis, more specifically Monte Carlo simulation, is a common step in analog and full-custom digital tool flows, but today most designers typically use a Monte Carlo simulation to come up with a parametric yield for their designs. The big problem is that after they run simulation and get the distribution, they don't really know which parts of the design are contributing to that distribution and what, if anything, they can do to improve that distribution without negatively impacting other parts of the design. Indeed, sometimes a small change in a design can result in a big boost in performance. Other times, a small change can cause big problems in other areas of the design.

Unlike standard digital design, in which designers have to deal with a handful of design specifications and variables, such as power, timing, yield, and signal integrity, plus interdependence among those variables, designers working at the transistor level typically have hundreds or thousands of variables to deal with, according to Amit Gupta, Solido's cofounder and CEO. Transistor-level designers typically have to balance specifications such as gain, phase margin, slew rate, CMRR, power dissipation, offset voltage, offset current, bias current, gain bandwidth, and settling time for each transistor, he noted.

"You have to account for these simultaneously, he said. "You can increase your phase margin and worsen your gain, or increase your gain and worsen your phase margin." On top of that, environmental effects impact a design. "If you have voltage, temperature, and load conditions and you have high, nominal, and low conditions for each of those, you permute out all the different variations of that and you have 27 different combinations of environmental effects that need to be considered simultaneously," Gupta said. On top of these complications, transistor-level designers also have to account for global statistical variations such as delta length and delta width; account for device variables such as length, width, and multiplier; and then account for local statistical variations such as flatband voltage, n substrate, delta length, and mobility.

"That's not for just one transistor," he said. "It's for all the transistors and all the devices. When you add up all these effects impacting your design simultaneously and all the considerations that the designer needs to consider simultaneously, there are literally thousands of different variables that need to be considered."

To deal with these thousands of variables, designers typically design within the boundaries of worst-case process corners, Gupta said. Doing that usually ensures that you hit yield margins but can also leave a great deal of performance, power savings, or other desirable effects on the table. Getting more performance or lowering the power consumption of your circuit while hitting yield can help designers give their companies an edge over the competition. That's where Solido believes it can help.

The company has come up with a five-part tool suite that will help users perform a relatively fast but thorough statistical analysis of a transistor-level design; point out areas that could improve the timing of the circuit; show the impact of those changes on different design variables; and then help designers implement those changes to squeeze better yield out of their designs while still meeting all other design requirements.

The engines in the SolidoStat offering are: SolidoStat Sampler, SolidoStat Characterizer, SolidoStat CircuitEnhancer, SolidoStat TradeoffAnalyzer, and SolidoStat Visualizer.

The Stat tool suite works with any of the big EDA vendors' Spice simulators, including Synopsys' Hspice, Cadence's Spectre, and Mentor's Eldo. Users will run multiple Spice simulations and then run the SolidoStat Sampler. The Sampler tool employs parallel processing and proprietary sampling algorithms to speed Monte Carlo simulation, accelerating it by 3 to 5×, according to Solido. Running static analysis on Spice deck data, the Sampler algorithms create a parametric yield number and a distribution. If the yield is not good, users can then activate the SolidoStat Characterizer, which will take a sampling and, using patent-pending algorithms, pinpoint sources of yield and performance loss in the design, zeroing in on transistor, resistor, and capacitor geometries that designers can change to improve the design.

"If there are problems, users can start characterizing their design to find out what's causing the physical distribution, which process variables are problematic, which specifications are problematic, which environmental conditions are problematic, and so on," Gupta said. "It helps designers narrow down the problems in their design so they only have to look at a few variables rather than a few thousand variables."

Once they've narrowed down the field to the problem areas, users can activate the TradeoffAnalyzer, which helps them determine whether they can trade specifications for improved yield. "It may say, for example, 'If you relax your gain and phase margin by 5%, you can get a 5% to 10% improvement in yield,'" Gupta said.

Users can then activate SolidoStat CircuitEnhancer, which lists features and suggests sizing alternatives for those features to optimize yield. Designers can then pick which features they want to adjust, make those fixes, and run the Sampler again to check that yield is optimal.

The suite runs statically and mines data from the Spice simulation database, Gupta noted. Thus it does not require users run a full Spice simulation and Monte Carlo analysis between each step.

On top of these tools, Solido has built a tool called SolidoStat Visualizer that converts the raw data from all the Solido analysis engines into dynamic visual representations.

The suite can run analyses on several thousand circuits, Gupta said.

SolidoStat pricing starts at $50,000 to $200,000.

Gupta and Trent McConaghy, Solido's chief scientific officer, founded Solido in January of 2005. Gupta and McConaghy previously founded Analog Design Automation, which was purchased by Synopsys in 2004. Solido's CTO is Patrick Drennan, former distinguished technical staff member at Freescale Semiconductor. The Stat technology came out of ongoing research being conducted by McConaghy and K.U. professor Georges Gielen at K.U. Leuven University in Belgium. To date, the company has raised $10 million in Series A and B funding.