Toppan, CEA-Leti to study double patterning

By Ann Steffora Mutschler, Senior Editor -- Electronic News, 9/18/2007

To extend 193-nm lithography to next-generation semiconductors, Round Rock, Texas-based photomask provider Toppan Photomasks Inc. and Grenoble, France-based technology R&D organization Electronics and Information Technology Laboratory of the French Atomic Energy Commission (CEA-Leti) reported today that they will explore double patterning techniques under a joint development agreement.

Double patterning is a resolution enhancement technique (RET) that effectively doubles the pitch of lithography. It was added to the ITRS roadmap in 2006 and is viewed as a leading technology option for extending 193-nm immersion lithography to the 32-nm process node while using existing tools, and is also viewed as a bridge to extreme ultra-violet (EUV) lithography technology, which is not expected to be available for volume production until approximately 2013 or later.

To address the challenges to making double patterning available to chip makers, CEA-Leti has formed a consortium, which Toppan will participate in, to help its partners achieve their internal technology goals and to support the ITRS.

Franklin Kalk, executive VP and CTO of Toppan explained that understanding the challenges of double patterning such as CD and placement control and the additional requirements this technology places on mask manufacturing is key to successfully implementing a double patterning strategy for customers.

“Our partnership with CEA-Leti combines our OPC models, OPC application to patterns and advanced mask manufacturing with a leading-edge research institute's proven expertise to assure that photomask technology for double patterning is available when our customers are ready for it,” he added in a statement.

In dealing with double patterning challenges currently, chipmakers are dealing with overlay, critical dimension (CD) control by RETs, and design decomposition into A and B layers.

"From a pure lithographic concern, overlay capability to build a composite pattern on the wafer is a requirement that connects the mask writer, mask metrology, scanner optics, and scanner stage in a very tight error budget," Toppan’s Craig West, director of applications explained.

For 32-nm half-pitch (HP) double patterning (DP), mask random errors in placement (registration) will have to be at or below 3-nm at the 4X reticle plane, he continued. The challenges for the scanner are also impressive with extreme requirements on every component that affects overlay.

DP will operate in a low k1 regime due to maximized NA for water immersion (NA <= 1.35).  This constraint on NA will continue to drive CD concerns with high mask error effects (MEEF) and require reticle CD uniformity to remain a key requirement.  Toppan said it is exploring new mask film stacks which may contribute to better litho process margins.

As well, Toppan said it will push OPC and RET methods to new capabilities for the low k1 printing to sustain process window margins as a counter to variation from more steps in the wafer flow.

More holistically, West noted that the device design and layer features must follow restricted design rules (RDRs) to allow the pattern to be segregated as a function of pitch into A and B patterns.  The two pattern subsets will then become the A and B masks of DP lithography with the final composite layer integrated at the wafer plan.  Stitching back together contiguous features is an option that is being tested and may give some freedom back to design and limit RDRs if successful, West said.

The companies believe their collaboration is very timely to address DP. Joint R&D from 2007 to 2009 will continue to be used to close gaps, demonstrate results, and broaden the mainstream industry consensus that DP is the best solution for 32-nm HP production. The 2009 ITRS Roadmap update will be an interesting checkpoint in DP progress.  As of today, high-volume manufacturing use of DP on memory products like flash seems likely by 2011, perhaps sooner if the pace of development continues, West added.

In terms of implementing the technology, CEA-Leti and Toppan said they share the objective of high-value commercial success in DP applications with resulting intellectual property and know-how available to leading semiconductor manufacturers under appropriate business terms.

“Key components in the success factors for DP will all be tested with the comprehensive resources of CEA-Leti added to the enabling contributions planned by Toppan for mask technology and RET applications,” West explained, with interim results and progress to be jointly published over the course of the JDP to mark milestones and innovations in all aspects of DP.

The Toppan-CEA Leti partnership is one of several double-patterning development projects that Toppan is participating in, and will leverage Toppan’s global manufacturing and research facilities.

The photomask fabrication and analysis will be done at Toppan's facility in Dresden, Germany.