Op-amp integrators can ramp to saturation, and a capacitor-discharge switch can reset them. Alternatively, you can input-switch them to ramp up and down in triangle-waveform-generator applications. Much searching through online “cookbook” circuits turned up no means of ramping an op-amp integrator to hold at a preset constant voltage level. This Design Idea describes a single-supply op-amp circuit that outputs a rising or falling linear-voltage ramp in response to a step change of a positive dc-input voltage of 0V to V_CC. The output ramp’s dV/dt slope is adjustable to 1V/minute with the values in Figure 1, is independent of the input-step amplitude, and terminates at a constant dc level approximately equal to the input-step voltage. Any further change in the dc-input voltage causes the output to ramp up or down at the preset dV/dt to the new dc-input voltage. In effect, this circuit is an amplitude-bounded constant-slope integrator.

The circuit uses a rail-to-rail I/O quad op amp, the National Semiconductor LMC6484. The rail-to-rail feature makes it easy to use, the low input leakage is great for long-time-constant integration, and the 3-mV maximum input-offset voltage is respectable. Potentiometer R₁, a linear taper, sets the input voltage for final output voltage after the ramp ends. IC_1A’s output is in saturation at V_CC or ground while the output is ramping down or up, respectively.

Nonpolarized capacitor C₁ and potentiometer R₂, a linear taper, determine the time constant of integrator IC_1B. The adjustment range is 0.5V/msec to 1V/minute. The reference bias for IC_1B is 108 mV, which you derive from IC_1D as a unity-gain buffer for divider R₇ and R₈. R₆ ensures that you do not exceed IC_1B’s input current when you turn off the power, that C₁ discharges through IC_1B’s input and output diodes, and that IC_1B’s output does not excessively load back into IC_1D’s output with R₂ at a minimum.

R₃ and R₄ divide the saturated IC_1A’s output to approximately 100 mV unloaded above or below the 108-mV bias. This division causes approximately 20 mV to drop across R₅ to slew IC_1B upward or downward at the integration rate that C₁ and R₂ set; 20 mV is comfortably above the op amp’s possible 3-mV input-offset voltage to minimize offset effects. When IC_1B’s output-voltage ramp reaches that of the input voltage from the R₁ wiper, IC_1A comes out of saturation and rests at approximately 2.5V, providing the loop-negative feedback to maintain integrator IC_1B’s output equal to the input voltage. This action sets the boundary on the integration ramp’s terminal voltage. IC_1C can be spare, or, as the figure shows, you can drive it with a triangle-wave signal to convert IC_1B’s dc level or ramp to a corresponding PWM (pulse-width-modulated) signal for a motor-drive circuit (not shown).

R₅ eliminates differential errors arising from bias-resistor tolerance, and it provides a compromise between IC_1B’s 3V maximum input-offset voltage at 25°C and 20-mV input amplitude to allow the slowest dV/dt. The values in the figure result in a maximum time of approximately 1V/minute, or 5 minutes at V_CC of 5V to reach full speed. If you require longer times, you can raise V_CC to 15V with adjustments to the bias resistors or raise C₁’s value by using parallel nonpolarized capacitors. Alternatively, you could raise R₂’s value, although selection is sparser for potentiometers with values greater than 1 MΩ.

If your application does not require a long time constant or if you use the aforementioned methods to increase the time constant, you can eliminate R₅ at the expense of a higher level differential input to IC_1B and correspondingly faster integration. You could also eliminate IC_1D and the R₇-R₈ resistive-bias divider that connects directly to IC_1B’s Pin 5, but resistor tolerance becomes more critical to minimize differential error (reference 1 and reference 2).