IMEC extends sub-32-nm research projects

By Colleen Taylor, Contributing Editor -- Electronic News, 10/15/2007

Belgian research center IMEC, which has been keeping busy in recent months with a flux of new partnerships and technology developments, announced today two separate steps forward on research aimed at pushing chip technology to 32-nm and below. 

In its first announcement, IMEC said today that it has launched research on next-generation DRAM metal-insulator-metal capacitors (MIMCAP) process technology as part of its (sub-)32nm CMOS device scaling program, which it says will allow it and its partners to address the material and integration requirements to scale DRAM MIMCAP to future technology generations.

In order to scale DRAM towards the 50-nm node and beyond, MIMCAP dielectrics require materials with a higher dielectric constant compared to current industrial materials, IMEC said. By mid 2008, an effective oxide thickness of 0.5-nm is targeted for the MIMCAP dielectric in the sub-50nm technology node, going down to 0.3-nm in 2009 for the sub-45-nm node. IMEC said that scaling the dielectric equivalent oxide thickness while attaining very low leakage currents is one of the major bottlenecks DRAM industry is facing; the center said its program is addressing this challenge.

The DRAM MIMCAP sub-program is part of the CMOS device scaling program within IMEC's (sub-)32nm CMOS research platform. The platform brings the top five leading memory suppliers -- Hynix Semiconductor,  Elpida Memory, Micron Technology, Qimonda and Samsung Electronics -- together with major logic IDMs and foundries.

In its second announcement today, IMEC said that it and the Microsystems Packaging Research Center (PRC) at the Georgia Institute of Technology have extended an invitation to interested parties from global industry to join their advanced research program on next-generation flip-chip and substrate technology.

According to the PRC and IMEC, the program addresses the key 'IC-to-package to board' packaging interconnect issues for 32-nm ICs and beyond. Together with their industrial parties, IMEC and Georgia Tech said they will explore, develop and invent new solutions to interconnect high-density ICs with very tight I/O pitches (down to 40-20µm peripheral) to low-cost packages and printed circuit boards. The program targets novel packaging approaches to reduce the mechanical stress on the IC after packaging and assembly.

The groups said that the 2-year program is open for the entire supply chain including system companies, IC manufacturers and assembly houses.

"We are excited to start this unique open program with PRC where we intend to bring together 20 to 30 expert researchers from industry and academia worldwide;"  Eric Beyne, program director of interconnect, packaging and systems integration at IMEC, said in a statement. "Only by joining expertise and know-how from leading players in the packaging and semiconductor field, we will be able to realize highly reliable solutions beyond the traditional flip-chip interconnections."

Financial details of IMEC and Georgia Tech's involvement have not been disclosed.