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Plugging hardware-based compression into a server
Prying Eyes gets an early look at a forthcoming PCIe-based hardware accelerator for the open-source GNU-zip algorithm.
By Ron Wilson, Executive Editor -- EDN, 11/22/2007
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1. The support: You have to feed an SRAM-based FPGA, even in a small system. Here, a CPLD and a NOR-flash part do the job. This combination is an Altera reference design that allows the board to hold two complete configurations for the Arria GX. This approach allows customers to experiment with the DMA logic and DDR-interface control.
2. The system interface: Comtech AHA uses an Altera FPGA to implement both the PCIe-interface logic and a DMA engine with scatter/gather capability to feed both the 3610s and keep them running.
3. The power: A Linear Technology switching dc/dc converter steps down the 12V supply from the PCIe connector to 3.3V for three Enpirion buck regulators, which in turn provide 2.5V for SSTL (stub-series-terminated-logic) I/O and 1.2V for core logic to the FPGA and Comtech AHA chips.
4. The crunchers: The AHA 3610s are numerical processors that do the gzip computations. Using internal buffer memory, they can work directly from the host server or the PC’s main memory. The data interface is a parallel pair of 16-bit DDR-DRAM interfaces, allowing each chip to compress or decompress data at 2.5 Gbps, with the equivalent of gzip-9 (high-effort) software-compression results.
