News and New Products

FPGA-design environment squeezes power consumption

By Maury Wright, Editorial Director -- EDN, 11/19/2007

EDA tools for FPGAs and ASICs commonly include optimization capabilities for timing and gate efficiency, but Actel claims that its new Libero Version 8.1 package is the first FPGA development tool to include low-power-optimization capability. The company has been promoting the miserly static- and dynamic-power consumption of its flash-based FPGAs, and the software tool allows designers to achieve additional power savings. Company Chief Executive Officer John East points out that not only mobile products, such as cell phones, but also medical and industrial products run on battery power and demand low power consumption.

Libero 8.1 attacks power consumption in four ways. First, the tool offers the aforementioned power-optimized-layout option, which the company claims can cut dynamic-power consumption by 30%. Second, the tool allows designers to analyze power profiles, such as active and sleep modes, and estimate battery requirements. Third, the tool can run an analysis on an FPGA layout and provide power-draw requirements for portions of the design, such as clock domains. Moreover, the tool can perform a cycle-accurate power analysis. Finally, a switching-analysis option can identify hazards or spurious signal transitions that waste power.

Actel offers a Platinum edition of Libero 8.1 for $2495 for Windows or Linux. A more feature-limited Gold edition is free for Windows. The company also has just announced what it claims are the smallest FPGAs on the market. The newest Igloo family members measure 4×4 mm. Prices for the 30-000-gate AGL030 start at $1.50 (volume quantities).